← 返回

2026.09.29 | Substack | Memory | SKHY DRAM on Logic & Bonders

原标题：SK hynix's DRAM on Logic: Who Stacks It, and Who Buys the Bonders?

#memory #semis

Substack · 2026-09-29

$000660 $005930 $MU $TSM $QCOM $BESI $AMAT | The next bonding demand after HBM, and who buys the bonders (Advanced Packaging, Part 3 of 3)

TL;DR

Contents

  1. The Question of Whether 4-High or 8-High Is Enough2. Is Stack Height Taking a Break?3. Checking Against the Last Map4. DRAM Comes Back on Top of Logic5. Why the Bonding Is Hard6. Who Stacks It7. What to Watch on the Equipment Side8. Closing9. References

1. The Question of Whether 4-High or 8-High Is Enough

At the afternoon packaging roundtable of the SK hynix Global Forum, held in the US on September 18, HBM stack height came up in the later part of the Q&A. An audience member asked what the panel made of the recent talk that 4-high or 8-high HBM is optimal.

The speaker answered that a SemiAnalysis post from the previous week laid it out well. Its analysis is that as token counts grow, the sweet spot between bandwidth and capacity moves toward lower stack heights, and the speaker agreed with that analysis, saying the company’s own memory-systems people already know this. The speaker added that the steady rise in stack counts should be seen as having slowed a little, that this is simply where things stand for now, but that it probably isn’t permanent. The same answer went on to 3D stacking, putting DRAM on top of logic.

I read that answer as a sign that the question has moved. Since the speaker admitted the slowdown and denied that it is permanent, the question left is less how high to stack HBM than where to stack DRAM.

The official wording runs a little differently. In a post on the TSMC event published on September 28, the SK hynix newsroom wrote that HBM keeps raising its stack count and bandwidth with every generation, which makes close ties with packaging essential [1]. Put the company’s public wording next to the roundtable answer, and the picture is roughly of a company that isn’t giving up the stack-count race but is separately looking for what comes next.

The event was an invitation-only session that doubled as recruiting, so I didn’t get the slides. As in parts 1 and 2, every fact that carries a source number was checked against public material, and anything I only heard in the room is flagged as such. In part 1 I wrote that part 3 would be about who stacks and who buys the bonders. If DRAM goes on top of logic, who buys the bonders? Even if a memory maker supplies the DRAM, there’s no guarantee it also does the final bonding, and following the public stacking cases turns up some clues. After part 2’s 2.5D, this is the 3D story of stacking upward.

2. Is Stack Height Taking a Break?

Let’s start again from SK hynix’s public roadmap as laid out in part 1, SK hynix’s Four Packaging Paths: Where Is the Fight After HBM?. The roadmap slide shown again in the August 23 Hot Chips talk (its footer credits ISMP 2024) put 8-high and 12-high in mass production, 16-high in parallel development with improved MR-MUF and hybrid bonding, and 20-high and above at the research stage with hybrid bonding alone [2]. MR-MUF is SK hynix’s current method: it stacks chips with small bumps between them and then fills the gaps with a liquid protective material. Hybrid bonding joins copper pads directly, with no bumps.

The case for lower stacks was made by SemiAnalysis in a September 13 post [3]. Going by the free section, the gist is that in decode (the part of inference that generates tokens one at a time), cost per unit of bandwidth and cost per token are lowest at 4-high. Bandwidth per HBM4E stack is the same regardless of height, and by their own model, 8-high and 12-high cost a little over 10 percent and about 26 percent more, respectively, at the system level than 4-high, while throughput rises by 10 percent at most [3]. These are calculations for a specific rack and model, so I’d be careful about generalizing.

NVIDIA has published few official numbers so far. What NVIDIA has stated directly is only that Rubin uses up to 288GB of 12-high HBM4 per GPU [4]. For the next generation, Rubin Ultra, TrendForce reported in early August that NVIDIA had widened its evaluation to include 8-high HBM4E as well as 12-high and 8-high HBM4, and that the final spec had not been set [5]. Taiwan’s Commercial Times, citing a Morgan Stanley supply-chain survey, expected the spec to be set before the end of the third quarter [6], but as of September 28 I found no confirmed announcement or report. A figure of 192GB per GPU is also going around, but it is SemiAnalysis’s own reporting, and NVIDIA has never confirmed it [3].

In the roundtable talk, thickness came up first. The explanation was that within today’s thickness spec, 16-high and 20-high are close to the limit; going to 20-high or 24-high may need new technology, and another route is a large-area package that fills out capacity with more HBM stacks per package. Simply raising the stack count is a matter of setting an internal process baseline and qualifying it, the speaker said. With large-area packages, though, problems that never showed up in small packages surface in the bigger ones, and TSMC’s approach differs from other companies’, so each one has to be matched separately. We also heard that the DRAM die thickness in MR-MUF stacks started at 50 micrometers, which even people inside the company were skeptical about at the time, and is now close to 30 micrometers. If part 1’s 0.9x cut in chip thickness is the step for one generation, from 12-high to 16-high, this is progress built up over several HBM generations.

Here’s my view. SemiAnalysis’s 4-high logic is a calculation aimed at inference, and specifically at cost per token in decode, and the original piece itself acknowledges up front that pre-training is far more sensitive to capacity [3]. The speaker also said bandwidth and capacity trade against each other, so large capacity will be needed at some point. So I think that on the unit cost of decode alone, lower stacks win, but that capacity-hungry workloads could split off into a separate product line that uses taller stacks. Measured against the path laid out in part 1, the move to 16-high with existing methods has slowed a little, which is the opposite of 20-high and above being pulled forward.

3. Checking Against the Last Map

On September 17, when I ranked hybrid bonding equipment companies by score in [[Investment Map] 22 Listed Companies in the Hybrid Bonding Value Chain, I judged that the stretch before memory adoption would be long and put a 1.5 weight on two scoring axes, logic and delay. Only eleven days have passed, so none of the dated checkpoints has come due, but when I pulled together the timing records behind that judgment again, they fit into a single table.

Starting with the 2024 records: an SK hynix packaging executive reportedly said at a November 2024 conference that hybrid bonding would be used from HBM4E, at a time when HBM4E mass production was planned for 2026 [7]. There was also an October report that Samsung Electronics had shown, at a 2024 conference, a roadmap applying hybrid bonding to HBM4 for mass production in 2026 [8]. Bonder maker BESI wrote in its 2024 Investor Day deck that memory adoption had slipped a year, to 2026 [9], and in this June’s deck it named 16-high HBM4E as the first insertion generation and wrote that a leading customer is preparing for high-volume manufacturing in 2027 [10].

Here’s where things stand now. Tom’s Hardware reported on the August Hot Chips talk that hybrid bonding would have a hard time making it into HBM4E, but according to the same article, the Hot Chips presenter didn’t name a target generation, and the company has not yet decided which product gets it first [11]. Two days later, a column by an Inha University professor published in the SK hynix newsroom judged that full adoption is most likely to come with HBM4E or HBM5 [12]. Market research firm Counterpoint expects SK hynix’s full-scale hybrid bonding production in 2029-2030, when HBM5 arrives [13]. Samsung said on its January earnings call that it plans partial commercialization at the HBM4E stage [14], and a July report said the company internally sees large-scale production becoming possible in 2030 [15].

Hybrid bonding in HBM moved from 2026 to 2027, and wider adoption is now projected for 2029-2030. Table comparing each company’s 2024 roadmap with where it stands in September 2026

Put in a table, the records show that the 2026 both memory makers were naming in 2024 has become, in BESI’s reckoning, a leading customer’s 2027 production. BESI’s August deck kept that sentence and only added the word “Anticipated” to the title of its first-insertion slide [16]. The 2029-2030 date for wider adoption is a projection from market researchers like Counterpoint. Because the two numbers come from different forecasters and different products, they’re hard to tie into a single production schedule, but they point the same way: the gap between first use and wide adoption is getting longer. I spent a good while digging through 2024 conference coverage to fill this table, and the window when both companies were naming the same 2026 turned out to be shorter than I expected.

In my September 17 piece I read the Hot Chips talk as saying existing methods would carry through HBM4E. A guest column in the same company’s newsroom saw HBM4E or HBM5 as the likely entry point, and BESI is talking about a leading customer producing 16-high HBM4E in 2027. BESI’s third-quarter results on October 22 should give the first clue as to how those two line up. I’m leaving the 1.5 weight as is. When I pulled the evidence together again, the case that the gap to wide adoption is lengthening came out even firmer, so I’d say the call that the delay stretch would be long was right, to a degree.

4. DRAM Comes Back on Top of Logic

The roundtable speaker recalled that when the first generation of HBM was being developed, the structure the customer originally brought was 3D, but it ran too hot, so the design fell back to 2.5D. I mentioned this in part 1, and the reason that picture has come back is energy per bit. On a slide AMD showed in its ISSCC 2023 keynote, moving one bit of data costs about 12 picojoules for a memory module (DIMM), about 3.5 picojoules for HBM on an interposer (an intermediate substrate that holds the chip and the HBM side by side), and about 0.2 picojoules when chips are hybrid bonded one on top of the other [17]. In the panel discussion, too, we heard that trimming the energy spent on the interface circuitry (PHY) that DRAM and logic use to exchange signals under an agreed spec would raise efficiency. On the customer side, it’s just as the keynote remark in part 1 put it: since this spring, customers have started asking for this structure almost as if on cue.

At TSMC’s April symposium, SK hynix put 3D Stacked DRAM on Logic, which stacks DRAM vertically right on top of a logic chip, on its roadmap and wrote that it is particularly well suited to on-device AI [18]. The company’s public materials that I checked through September 28 give no year for this structure. The final prospectus filed with the SEC for the July US listing and the 21 Form 6-K filings since then don’t use the words “hybrid bonding” or “DRAM on logic” either; there is only a broad sentence about investing in custom base dies and advanced stacking techniques for next-generation HBM [19][20].

On why DRAM on logic is hard, the roundtable explanation was more concrete than the public material. From HBM4, SK hynix makes the base die on TSMC’s logic process, and it stacks the core DRAM on top with its own stacking technology, MR-MUF [21][22]. The speaker said this is closer to a minor change, moving a base die the company used to design itself onto a foundry design.

DRAM on logic is a different matter. According to the speaker, DRAM so far hasn’t used the low-k dielectric found in logic wiring (an insulating film with lower permittivity to cut signal delay); the process design changes completely depending on whether the logic die faces up or down; and the concepts behind aluminum pads and the layers that use low-k are different too, so there’s no way to know what problems will come up. We also heard that this only works if you open up information with your partners, down to the recipe level.

This much can be drawn from public material. In the paid section, I first walk through why this structure is hard from an engineer’s point of view, then put the public cases where DRAM has been bonded, or was announced to be bonded, onto logic into one table and compare who made the logic with who did the bonding. In the “who bonds” column of that table, only the SK hynix cell is empty, and how that cell gets filled will decide where the bonder purchase orders go. After that, I also lay out which process I’m watching instead of the bonders.

This Substack is reader-supported. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribed Thanks for reading! This post is public so feel free to share it.

Share

5. Why the Bonding Is Hard

The first thing I get stuck on as an engineer is die orientation. With logic on the bottom, the DRAM takes the logic’s heat directly. DRAM has to rewrite its data (refresh) more often as temperature rises, so it is sensitive to heat. Put the logic on top and the heat source moves closer to the cold plate, but now the paths for power and signals become the problem. d-Matrix’s accelerator, shown at Hot Chips in August, puts the logic on top and custom DRAM underneath (bonded with 36-micrometer-pitch bumps rather than hybrid bonding [23]). Because the DRAM die doubles as the interposer, hundreds of watts of power going into the logic, along with PCIe and die-to-die signals, pass through the DRAM’s TSVs (vertical electrodes drilled through the silicon) [24]. d-Matrix designed the DRAM to run at a 105°C junction temperature, and according to the company, data retention of 32 milliseconds at the standard 85°C drops to 4 milliseconds at 105°C, so refresh has to happen eight times as often [24]. Either way, the DRAM design has to change to fit the logic.

How much heat matters shows up in imec’s IEDM 2025 work. Put four 12-high HBM stacks straight onto a GPU, and the GPU’s peak temperature hits 141.7°C, more than 70°C above the 2.5D case (69.1°C) under the same cooling. Applying mitigations one after another, among them stack merging, a halved GPU clock, heat-conducting silicon and double-sided cooling, brings it down to 70.8°C, but the clock-halving step slows training by 28%. imec still found that 3D delivers higher throughput per package area than 2.5D [25]. These are simulation results, not measurements on a built chip.

imec IEDM 2025 3D HBM-on-GPU thermal simulation. Package peak temperature for the 2.5D baseline, unmitigated 3D stacking and after each mitigation step. Source: imec press release, December 8, 2025

So has the heat problem that stalled 3D stacking about 15 years ago finally been solved? Going by the simulation alone, it is solved once several mitigations are layered together. But those mitigations include lowering the clock and system-level changes like double-sided cooling, so it’s still hard to call it a problem solved at the chip level.

The bonding step itself has a temperature limit too. DRAM’s data retention degrades when the chip is baked at high temperature for a long time, so it reportedly needs a lower temperature than hybrid bonding’s standard anneal of 350°C for two hours [26]. Panelists at the ECTC 2025 hybrid bonding special session also agreed that HBM and 3D DRAM need bonding below 250°C, which calls for low-temperature copper or new dielectric materials [27].

The last hurdle is test. Bond whole wafers (W2W) and the bad dies get bonded too, and yield losses compound with every layer. Management at PieceMakers, a Taiwanese DRAM design company, said that at 80% yield per layer, a four-layer stack falls to about 41% and an eight-layer stack to about 17%, and that test and repair are needed before bonding, after bonding and after attaching to the logic [28]. As we saw in part 2, SK hynix’s In-House 2.5D: Validation Comes Before Commercialization, finding the cause of an HBM failure inside a 2.5D package is already hard, and in 3D you can’t even pull the failed DRAM off the logic.

The picture the speaker drew, framed as personal speculation, was 3.5D. Because heat makes it hard to add capacity to DRAM on logic, the bandwidth-hungry part would go to DRAM on logic, and capacity would be filled by tall HBM or HBF (high-bandwidth flash, NAND stacked like HBM) placed alongside. In the industry, 3.5D usually refers to an AMD MI300-style structure that places stacks of logic chips next to HBM, so please don’t mix the two up just because the name is the same. The speaker’s picture extends to 3D the split between a bandwidth slot and a capacity slot that I described in section 2.

6. Who Stacks It

The roundtable speaker said logic has to come from outside and today that’s mainly TSMC, and that SK hynix could either take in logic and put memory on it or hand memory to TSMC and let TSMC stack it. Which combination it is determines both technical maturity and the business model, the speaker explained. So I looked through public material for which way the company would go, and none of the three big memory makers has said who will bond its DRAM onto a customer’s logic. Instead, I gathered the cases already out there.

Taiwanese media reported that Powerchip (PSMC) announced in 2020 that, working with AP Memory at an overseas customer’s request, it had mass-produced an AI chip bonding a logic wafer to a DRAM wafer and delivered it to the customer [29]. The article does not say which company made the logic wafer for that chip, though, and Powerchip’s chairman explained that because logic applications vary, the company has to work with several logic foundries [29]. The chip AP Memory demonstrated the following year had Powerchip making custom DRAM wafers while TSMC handled the logic and the 3D stacking service [30], but the announcement did not state how they were bonded. In 2023, UMC announced a project to stack Winbond DRAM and logic wafer to wafer, and listed wafer-to-wafer hybrid bonding as its own role [31]. It was more a platform announcement than a volume product.

PieceMakers, whose largest shareholder is Nanya and which registered on Taiwan’s Emerging Stock Board on September 16, pointed the same way. The president said the company doesn’t do TSV or hybrid bonding itself, and that these are mainly handled by the front-end fab (the plant that processes the wafers); the chairman added that the step of joining DRAM to the SoC (the main processor chip) is mostly handled by the SoC-side fab, while stacking multiple DRAM layers has to be looked at separately [32]. The company also explained that, depending on the project, additional partners with hybrid bonding capability may join [33].

The case for memory makers doing the DRAM stacking comes from Qualcomm’s HBC (Qualcomm’s AI chip structure that stacks DRAM vertically on top of the accelerator chip). In part 1 I wrote that who supplies HBC’s memory had not been disclosed, and by Qualcomm’s official materials that is still true. In late August, though, TheElec reported that Samsung Electronics and SK hynix would handle the DRAM stacking and that Qualcomm plans to work with TSMC on integration and packaging [34]. That division of roles is the reporter’s own summary; a Qualcomm executive, speaking at a conference around the same time, said only that because Qualcomm isn’t a memory vendor, someone else does the DRAM stacking, and that pulling it all together is done with the likes of TSMC [35]. Qualcomm has never disclosed HBC’s bonding method. When I covered HBC in July in Three Routes Around the Memory Wall: Qualcomm’s Stack, Nvidia’s 3 Bits, and What Remains, this box was empty too.

Where the logic maker is on record, the company that made the logic also did, or said it would do, the stacking. Table of logic maker, DRAM maker, bonding party, status and source type by case

Read the logic column and the who-bonds column of the table above together. Looking only at cases where the logic maker is known, I think the dividing line is less foundry versus memory maker than who makes the logic wafer and takes responsibility for integrating the stacking process. That’s what I mean in this piece by the side holding the logic wafer. In the AP Memory chip, TSMC took on both the logic and the 3D stacking service; in the Winbond project, UMC said it would handle both the logic wafer and wafer-to-wafer hybrid bonding; and PieceMakers’ management described it the same way. For Powerchip, all that can be confirmed is that it did the bonding itself, and since the source of the logic wafer isn’t stated, I left it out of the evidence for this judgment.

The limits are clear, too. The DRAM in the supporting cases is all Taiwanese specialty DRAM (Winbond, Nanya-affiliated, Powerchip custom DRAM), and there is no confirmed case yet of a foundry bonding DRAM from the three big memory makers. So this is my inference from the cases.

Memory makers are developing their own bonding, too. At the 2024 VLSI Symposium, SK hynix presented 3D DRAM research in which a wafer with cells stacked in five layers was hybrid bonded onto a peripheral-circuit wafer (the circuits that read and write the cells) and shown to work [36]. Samsung unveiled zHBM, a concept that puts HBM directly on top of an accelerator, and in the same press release promoted a one-stop service as a company with memory, foundry and packaging all in house [37]. But this is development capability; the ability to take in a customer’s logic and stand behind commercial yield and volume has not been confirmed. So I think who does the bonding is more likely to be decided by the side holding the logic wafer and by the customer’s choice than by technology.

One more thing to note: stacking DRAM on DRAM and bonding that stack onto logic can be separate steps. The multi-layer products PieceMakers described stack the DRAM first and then join it to the SoC [32], and HBC has the same structure going by the Qualcomm executive’s description [35]. In that case the memory maker builds the DRAM stack, and the side holding the logic wafer bonds it onto the logic.

SK hynix hasn’t said who will do the bonding, but it has signaled a direction. At TSMC’s April symposium, while presenting the HBM4 base die collaboration, it drew its roadmap outward from custom HBM to HBF and 3D Stacked DRAM on Logic [18]. A job posting its San Jose unit put up in early September seeks a lead to co-design the peripheral-circuit IP and logic die for 3D-stacked DRAM with US customers and to handle foundry verification as well [38]. As we saw in part 2, the roundtable speaker said the company won’t go where it would overlap with TSMC, and the work this posting assigns also stops at design and foundry verification.

The posting doesn’t spell out a division of roles in which TSMC does the bonding. If I apply my inference as is, then as long as the customer’s logic comes from TSMC, the bonding step is likely to happen on TSMC’s side, with SK hynix handling the DRAM and the design collaboration.

In the official TSMC materials I checked through September 28, I found no specific customer or business model for bonding other companies’ DRAM with SoIC (TSMC’s chip-stacking service). The closest thing is that the SoIC introduction page includes memory chips in its service scope [39]. This part stayed blank in the end.

In part 1 I wrote that if TSMC takes all of the logic-memory bonding, the subject of that map shifts from SK hynix to TSMC. If my judgment that the side holding the logic wafer does the bonding is right, most of the bonding step goes to TSMC, but building the DRAM stack likely stays with the memory makers. I see that as closer to a split, with DRAM stacking and logic integration handled by different players, than to TSMC taking everything.

7. What to Watch on the Equipment Side

In D2W hybrid bonders, which place chips one at a time onto a wafer, BESI is at the commercial stage with 21 hybrid bonding customers, counting the line it offers with Applied Materials [40]. ASMPT is sampling its second-generation tool with key customers [41], Hanmi Semiconductor is at the stage of releasing a second-generation prototype this year [42], and Hanwha Semitech is having its tool evaluated at SK hynix [43]. For W2W bonders, which bond whole wafers, EV Group, Tokyo Electron and SUSS are the main commercial platform suppliers. I laid out company-by-company details in the September 17 map.

If, as I judged in section 6, the bonding step moves inside the foundry, the foundry is also likely to buy the bonders that attach DRAM to logic (W2W for whole wafers, D2W for individual chips). But if the foundry hands this step to an OSAT (outsourced assembly and test company), the equipment buyer could change again. The bonders that build the DRAM stack would be bought by the memory makers.

On the W2W side, demand could arrive first regardless of DRAM on logic. That’s because structures that make DRAM cells and peripheral circuits separately and then bond them, like the SK hynix VLSI work above, show signs of moving past research and onto commodity DRAM roadmaps. A report on September 23 said Samsung had put this approach on the roadmap for its first sub-10-nanometer DRAM (citing anonymous sources; no company confirmation) [44].

Test burden also depends on the bonding method. D2W, which places chips one at a time, lets you select just the good dies before bonding but is slower, while W2W, which bonds whole wafers, is faster but bonds the bad dies along with the rest [45]. According to the Inha University professor’s column from section 3, hybrid bonding costs two to three times as much to manufacture as conventional flip-chip (flipping a bumped chip and attaching it) [12]. Reportedly, because it joins copper pads and dielectric directly with no bumps, the polished surfaces can’t vary by more than about 0.2 nanometers, and a single particle smaller than a micrometer can lift many pads at once [46]. That is why Onto, when it launched a new inspection tool in March, aimed it squarely at picking out sub-micron defects in CMP (the polishing step that flattens the wafer surface) and hybrid bonding [47].

Personally, I’ve been looking hard at test and inspection before and after bonding lately, more than at the bonders. It’s less that I have evidence they make money first and more that they are steps you can’t skip no matter who bonds DRAM onto logic or how. Electrical test and repair are needed before and after bonding and after attaching to the logic, as we saw in section 5, and since bonding whole wafers means you can’t pull the bad dies out before bonding, the burden after bonding actually grows. Inspection and metrology look at the bonding surfaces themselves. The test and inspection story from part 1 carries straight into 3D.

In numbers: on its second-quarter earnings call, BESI said one of the three memory makers is evaluating and another is starting evaluation [40]. On the inspection side, KLA management said on its July earnings call that new packaging technologies such as hybrid bonding are raising process control intensity, and that the SoIC and hybrid bonding demand it had long waited for is now starting to show [48]. Camtek said on its second-quarter call only that its inspection tools are moving into additional process steps including hybrid bonding, without breaking out related orders or revenue [49]. None of these comments addresses DRAM on logic directly, and right now demand is showing up for both bonders and inspection tools in the hybrid bonding market.

While writing this section I looked for filings or announcements of bonders bought specifically for DRAM on logic and found none. What this track carries today is a direction of demand more than orders.

8. Closing

For HBM hybrid bonding, the expected first production has slipped a year, and the gap to wide adoption is getting longer. Meanwhile a second demand track, DRAM on logic, has opened up. Nobody knows yet who will buy those bonders, but going by the public cases where the logic maker is known, I think the side holding the logic wafer is likely to take the bonding step while building the DRAM stack stays with the memory makers.

If one of the three memory makers formally says it will take in customers’ logic wafers and bond them in its own fabs, though, this judgment is wrong. The yardstick I set in part 1 also stays. If no named customer or design completion for SK hynix’s DRAM on logic emerges by the end of 2027, I’ll take it that half of Path 3 on the part 1 map was only a slide, and lower my expectations for how fast DRAM on logic reaches commercialization. Here, news only counts if the company or the customer states it directly. Reports on Qualcomm HBC’s suppliers, or SemiAnalysis’s report that SK hynix will supply stacking DRAM for NVIDIA’s next-generation inference chip LP40 [50], don’t meet that bar yet.

Here are the dates to check against.

Of what I heard at the roundtable, HBF and optical interconnect will get a separate piece of their own.

9. References

[1] SK hynix Newsroom: SK hynix at TSMC OIP 2026, Partner of the Year in 3DFabric-HBM Integration, 2026-09-28

[2] ServeTheHome: SK hynix HBM Packaging at Hot Chips 2026, 2026-08-23

[3] SemiAnalysis: Long Live the Short King: Why 4-hi HBM Wins, 2026-09-13 (secondary source, free section)

[4] NVIDIA Technical Blog: Inside the NVIDIA Rubin GPU Architecture, 2026-07-21

[5] TrendForce: NVIDIA widens Rubin Ultra HBM specification evaluation, 2026-08-04

[6] Commercial Times: HBM supply tight, Rubin Ultra configuration adjusted (citing a Morgan Stanley supply-chain survey; in Chinese), 2026-08-12

[7] etnews: SK hynix to apply hybrid bonding from HBM4E (in Korean), 2024-11-07

[8] TheBell: Samsung Electronics’ HBM4 hybrid bonding roadmap (in Korean), 2024-10-15

[9] BESI: Investor Day 2024 Presentation (p.50), 2024-06

[10] BESI: 2026 Investor Day Presentation (slides 30, 46), 2026-06-18

[11] Tom’s Hardware: Hot Chips 2026: SK hynix pushes hybrid bonding to HBM5 as AI memory hits 775-micron ceiling, 2026-08-24

[12] SK hynix Newsroom: Tech Note Ep.2 Hybrid Bonding (guest column by Prof. Seunghwan Joo, Inha University), 2026-08-25

[13] Seoul Economic Daily (English): SK hynix eyes HBM5 launch by 2029 with hybrid bonding (citing Counterpoint), 2026-04-06

[14] TheElec: Full transcript of Samsung Electronics’ Q4 2025 earnings call (in Korean), 2026-01-29

[15] TheElec: Samsung Electronics’ hybrid bonder production line at Pyeongtaek (in Korean), 2026-07-21

[16] BESI: Investor Presentation August 2026 (slides 36, 39)

[17] ServeTheHome: AMD Talks Stacking Compute and DRAM at ISSCC 2023, 2023-02-25

[18] SK hynix Newsroom: SK hynix at TSMC 2026 Technology Symposium, 2026-04-23

[19] SEC EDGAR: SK hynix Inc. Form 424B4 final prospectus, 2026-07-10

[20] SEC EDGAR: SK hynix Inc. filing index (21 Form 6-K filings, 2026-07-15 to 2026-09-18), retrieved 2026-09-24

[21] SK hynix: HBM4 product page (logic-foundry base die, 16-high Advanced MR-MUF)

[22] SK hynix Newsroom: From HBM to eSSD, 2026-07-08

[23] d-Matrix researchers: Early Silicon of Raptor (ISCA 2026 paper, author-hosted PDF, 36μm-pitch F2F microbump stacking)

[24] Tom’s Hardware: d-Matrix stacks its AI accelerator directly on custom DRAM (including the d-Matrix Hot Chips slide gallery), 2026-08-26

[25] imec: Imec mitigates thermal bottleneck in 3D HBM-on-GPU architectures (IEDM 2025), 2025-12-08

[26] Semiconductor Engineering: Gearing Up For Hybrid Bonding, 2023-10-23

[27] IEEE EPS Newsletter: Emerging Technologies TC, Hybrid Bonding (summary of the ECTC 2025 special session), 2026-03

[28] Tom’s Hardware: PieceMakers fuses DRAM stack directly to the processor using hybrid bonding, 2026-09-16

[29] Cnyes: Powerchip’s logic-DRAM wafer stacking breakthrough targets AI applications (in Chinese), 2020-08-18

[30] AP Memory: 3D integration of DRAM and Logic (VHM), 2021-08-24

[31] UMC: W2W 3D IC project announcement (Winbond CUBE), 2023-10-31

[32] NextApple: PieceMakers pre-listing briefing (in Chinese), 2026-09-07

[33] MoneyDJ: PieceMakers focuses on custom AI inference chips, aims for volume production next year (in Chinese), 2026-09-07

[34] TheElec: Qualcomm HBC memory partners and TSMC role, 2026-08-27

[35] Investing.com: Qualcomm at Deutsche Bank 2026 Technology Conference (transcript), 2026-08-26

[36] IEEE Xplore: A Three Dimensional DRAM (3D DRAM) Technology for the Next Decades (SK hynix, VLSI 2024 T17.3)

[37] Samsung Newsroom: Samsung Unveils Next-Gen 3D Memory Vision at FMS 2026, 2026-08-05

[38] SK hynix America job posting: Director of 3D Stacked Logic Design (Greenhouse, retrieved 2026-09-28)

[39] TSMC 3DFabric: SoIC technology page, retrieved 2026-09-28

[40] Investing.com: BESI Q2 2026 Earnings Call Transcript, 2026-07-23

[41] ASMPT: ASMPT Announces 2026 Interim Results, 2026-07-29

[42] Dailian: Hanmi Semiconductor to release second-generation hybrid bonder this year (in Korean), 2026-04-09

[43] TheElec: Hanwha Semitech hybrid bonder SHB2 Nano at SK hynix, 2026-06-10

[44] ZDNet Korea: Samsung Electronics’ D0a roadmap for its first sub-10nm DRAM (in Korean), 2026-09-23

[45] Semiconductor Engineering: Making Hybrid Bonding Better, 2026-03-02

[46] Tom’s Hardware: The current state of Hybrid Bonding in 2026, 2026-09-02

[47] Onto Innovation: Onto Innovation Launches Dragonfly G5 Inspection System, 2026-03-16

[48] Investing.com: KLA Q4 FY2026 Earnings Call Transcript, 2026-07-28

[49] The Motley Fool: Camtek (CAMT) Q2 2026 Earnings Call Transcript (call 2026-08-10, transcript posted 2026-08-17)

[50] SemiAnalysis: GTC 2026: The Inference Kingdom Expands, 2026-03-24 (secondary source, free section)

[51] Micron press release (GlobeNewswire): Micron Technology to Report Fiscal Fourth Quarter Results on September 30, 2026, 2026-08-26

[52] TSMC OIP Ecosystem Forum 2026 North America: online event agenda (TSMC event registration platform)

[53] Economy Tribune: report on 3D DRAM in 2029 and 115x at TSMC OIP (in Korean; single outlet, presenter not named), 2026-09-24

[54] Tom’s Hardware: TSMC details next-gen CoWoS roadmap, 24 HBM5E stacks by 2029, 2026-04-27

[55] OCP Global Summit 2026 event page · SEDEX 2026 overview

[56] TSMC Investor Relations: Financial Calendar, retrieved 2026-09-28

[57] BESI: Financial Calendar, retrieved 2026-09-28

[58] IEEE IEDM 2026: Session 11, NAND & DRAM (2026-12-15)

[59] Qualcomm: Qualcomm Unveils Comprehensive Data Center Roadmap for the Agentic AI Era, 2026-06-24

This article is an independent technical analysis published by PhotonCap, based on an engineering perspective. All content is derived from publicly available information and the author’s on-site notes, and remarks heard at the event are identified as such in the text. It is intended solely for educational and informational purposes. In other words, nothing in this material should be construed as a recommendation to buy, sell, or hold any specific securities. Please note this carefully.

The author may hold positions in the securities mentioned herein and reserves the right to trade such securities at any time without prior notice. Readers should conduct their own thorough review and research before making any investment decisions.

Share

Invite your friends and earn rewards

If you enjoy PhotonCap, share it with your friends and earn rewards when they subscribe.

Invite Friends