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2026.09.30 | TB | Semis | Samsung & TSMC Foundry Expert

原标题：Semiconductor Manufacturing Industry – Samsung Semiconductor & TSMC – Former VP at Samsung Electronics Co Ltd

#semis

Third Bridge · 2026-09-30

Client-led • 3 Sep 2026

Companies: A005930 KR, 2330 TW, NVDA US, TSLA US, INTC US, AAPL US, QCOM US, AVGO US, AMD US, MU US, A000660 KR

Expert Former VP at Samsung Electronics Co Ltd

Agenda

Questions

00:06:18] Can you give an overview of where Samsung is capacity-wise with 5-nano and 3-nano, along with the outlook for 2-nano and 1.4-nano?

Expert [00:06:34]: Actually, Samsung has seen a lot of trouble in the leading-edge logic foundry business. I think it's quite a long time. It's like 7-8 years. Samsung has been competing quite comparable with TSMC until 14-nano. I think that was somewhere like 2014-15 around those times. After that, the gap became widened. One of the biggest mistakes in Samsung, actually, that's a starting point of all the trouble and predicament in Samsung Foundry, the top management made the decision to introduce EUV first time in industry earlier than TSMC. That's actually just beginning of all the chaos, but that's a long story. Anyway, Samsung had trouble in yield improvement. Also, it's not just the PPA just getting behind the TSMC, but also a lot of thermal heating issue on the chip just causing some design flaw in the chip. That actually made a lot of trouble.

00:12:12] For 2-nano, did Samsung do backside power and gate-all-around at the same time?

Expert [00:12:22]: It's actually the transistor architecture is GAA, so gate-all-around. That's the second challenge that Samsung made to catch up. That's a model to catch up TSMC in achieving the technological superiority, but GAA was adopted from 3-nano. Meanwhile, TSMC still have FinFET from 3-nano. GAA adoption in Samsung is also first time in the industry, but that also turned out to be a good failure. Anyway, the BSPDN, the backside power delivery, Samsung is a little bit delaying those adoption. I think that is majorly adopted from the next node, 1.4-nano. There are some rumours that the BSPDN would be applied just later version or the later generation of 2-nano, maybe the last version of 2-nano. That would be possible, but major adoption is from 1.4-nano. TSMC, they said the TSMC is going to employ backside power delivery from their 16 Angstrom. 16 Angstrom is supposed to come out by end of this year, earlier than Samsung. Intel also is making PowerVia. That's their name. They said they already employed to 18 Angstrom process, if I'm right.

00:14:22] What do you think about Samsung's capacity plans for 2-nano? Is it planning any investments at 3-nano or 5-nano? Will it invest or build any capacity at 3-nano or 5-nano, or is it only going to invest in 2-nano?

Expert [00:14:50]: That's actually depending on the customer, but actually just leading-edge logic is just major volume for Samsung Foundry right now is 4-nano and the second is 5-nano. Even 7-nano is actually just decreasing these days. 3-nano is quite small from the beginning because it's a total failure. The 2-nano is increasing rather rapidly. The Taylor fab is not, the construction is not completed, but still there is a model fab in Hwaseong, which is called S3. They completed internal qualification of 2-nano as a model fab in S3, I think that was December last year. For example, the yield for the 3-nano in Samsung Foundry. There's two different type of 3-nano. The first version is 3-nano without SRAM, but the next generation was 3-nano with SRAM. 3-nano with the SRAM is more like a complete set of product.

The yield for first generation 3-nano without SRAM is actually quite improved to higher than 60% in yield, but second generation with SRAM because with SRAM is actually the overall process is getting much more complicated. The yield is still remaining about 30% even now for the 3-nano, but 2-nano, the rumour shows that only around the time they actually finished the internal qualification that was December last year, they reached the yield of around 30%. That's actually a lot better than 3-nano. Also, more recent report saying that that's actually keep improving and going over 50%, approaching to 60% now. That's actually quite better than 3-nano. Also overall performance and PPA, it looks like still behind TSMC, but the gap is getting close because until 3-nano, it was considered the gap between TSMC and Samsung is almost one generation, one node, but it looks like the 2-nano, the performance is getting close, more like half node difference.

Client [00:18:06]: Is this for 2-nano or 3-nano?

Expert [00:18:09]: 2-nano. 3-nano is still a big failure and low yield, but the 2-nano looks a lot better, not only in terms of yield, but also the performance. Still lower density of transistors and PPA also inferior, but gap is getting close.

00:23:06] Who is Samsung planning to fill capacity with? Tesla won't be 140,000 wafers per month of 2-nano.

Expert [00:23:15]: This is kind of long-term estimate because Samsung is expecting that… Samsung has mega deal, USD 16.5bn with the supply starting next year until 2033. That's a big volume, but Samsung also said that there are a lot of media reports keep going on, keep going up, keep coming up. Samsung has also said in the conference call that they expect more 2-nano customer win. Some of them in some testing evaluation, but the other is actually in active contract negotiation going on. Broadcom has come out much earlier. Samsung and Broadcom made MOU, I think that was last year. For now, the contract already made other than Tesla, not really a big customer, just AI chip company.

There's Preferred Networks. That's AI chip fabless company in Japan. It's not big, but not really small. It's a mid-sized company. It became quite famous in Japan. There are several others, starting up company like Rebellions, Ambarella and DeepX. Those are small companies, but anyway, Qualcomm announced that they actually completed design work with Samsung and some more active commercialisation discussions in progress. It's possible that actually some news will come out sooner or later. It's not just an evaluation or testing phase. It's actually more like commercial negotiation. It's not yet confirmed the volume awards, but it looks like active negotiation going on. The Broadcom is just occasional announcement for MOU, that's more like it's not just a leading-edge logic, but also including overall memory and HBM and advanced packaging through (inaudible). That's MOU with Broadcom, but that's very significant and quite potential, but still not a binding order yet.

Client [00:26:55]: It could be memory or many things, right?

Expert [00:27:02]: Yes. Volume allocation is still uncertain, but one of the big cause of increase in capacity, especially the 4-nano is the rapid increase of volume for base die for HBM4 these days. Samsung actually using 4-nano leading-edge process for their base die for HBM4. That's a very unique and special type of, more challenging decision they made.

00:29:47] What do you think about TSMC's plans for 2-nano over the next few years?

Expert [00:30:05]: For 2-nano?

Client [00:30:05]: Yes and 1.6-nano.

Expert [00:30:10]: 2-nano, they already started the production, it is Q4 last year. They actually started production in the model fab in Taiwan. I don't remember the name and moved over to the second fab. They are actually ramping up the 2-nano in two fab in Taiwan. Maybe I can find very quickly. 2-nano started production first time in Hsinchu fab 20, that was Q4. I think that was something around September or October.

00:31:27] Do you know what volumes should be at the end of the year?

Expert [00:31:56]: I don't have such a detail about Samsung, but TSMC says, N3, oh, it's actually, N3. There's a number for N3 and N2. N3 capacity is roughly about 150,000 wafers per month in H1 of this year, but it's actually increasing to 180,000 per month by only Q4 this year. That's what TSMC said. N2, 2-nano is actually about 50,000-60,000 wafers per month in H1 of this year. That's moving above 80,000 in early Q4 this year and increase to 100,000 wafers per month by end of this year. That's actually publicly announced. That's what I have.

Client [00:33:04]: 180,000 wafers per month for N3, 100,000 wafers per month for N2. What are your expectations for '27 and '28?

Expert [00:33:25]: It only shows over 200,000. I don't have the details.

Client [00:33:33]: For which nodes?

Expert [00:33:35]: For 3-nano and 2-nano as well because 3-nano is actually, slightly, gradually decreasing, but 2-nano is increasing more rapidly. It looks like both 2-nano and 3-nano will be over 200,000 next year. I don't have specific number.

00:35:06] What is the customer demand vs what TSMC can deliver?

Expert [00:35:30]: Actually, all the global customers are the customer of TSMC. I was looking at the customers for 3-nano in TSMC, and the majority is actually Apple.

Client [00:36:10]: For 3-nano?

Expert [00:36:11]: Yes. Majority is Apple. If Apple is actually the flagship product, the chips for flagship product is moving to 2-nano, but then that's cascading effect with 3-nano customers moving to 2-nano, 4-nano customers moving to 3-nano and 5-nano is moving to 4-nano, something like that. Still it doesn't mean that all the Apple is only using 3-nano for now and then just moving to 2-nano, just all the products moving to 2-nano. It's not like that. Only the chips for flagship product is actually just moving to 2-nano and the other is actually still remaining in the older node. It's not only the 3-nano, there's some 4-nano and 5-nano as well. Depending on the model. It's a wide range even in Apple.

00:37:49] When do you think Nvidia and Broadcom will move to 2-nano?

Expert [00:38:06]: I'm not really sure, but the latest node, the most leading-edge node is mostly occupied by the smartphone vendors, smartphone chip makers, so Apple and Qualcomm. Actually, Apple is mostly the major one. Qualcomm is also, their more high-end Snapdragon is going into 3-nano process nowadays. That's more the number one priority.

00:39:18] What is Rubin on?

Expert [00:39:21]: Rubin is supposed to go into 3-nano because Blackwell is 4-nano.

Client [00:39:32]: I think Nvidia is also the first to adopt 1.6-nano with backside power next year. What do you think?

Expert [00:39:45]: Yes, I also heard that, too because actually, just TSMC created a sub-node called 16 Angstrom. That's actually sub-version of 2-nano.

Client [00:40:06]: 2-nano with backside power to split up, right?

Expert [00:40:09]: Yes, with backside power. I think those kind of approach might expand more of the portion of 2-nano family because 16 Angstrom is more advanced node, generation of 2-nano. I think that might create some more room for other customers to go into the leading-edge nodes other than Apple. Nvidia is also becoming top company, even larger than Apple nowadays.

Client [00:40:51]: Is it the largest customer?

Expert [00:40:53]: Right. It's getting harder and harder to deny any request from Nvidia nowadays. Nvidia has more power.

00:41:07] Let's assume over the next 1-2 years, Nvidia moves its newest generation to 1.6-nano, and Apple moves a lot of volume to 2-nano or N2 and N1.6. Who backfills that 3-nano capacity? Is there still enough customer demand to move down from 5, 7, and 4 to 3-nano?

Expert [00:41:46]: Even now, those Nvidia's Rubin generation has already been released. I think that recently started production. Nvidia's Rubin and AMD's MI chip, MI GPU and Broadcom ASIC and Google and AWS and Meta, they also actually designed their own AI chip. These are the list, those actually increasingly moving to 3-nano even now. Those are major customers that's moving from 4-nano or older to 3-nano these days. From 4-nano to 5-nano to 3-nano, yes, that's actually during this year. Any other customer who also backfill 5-nano, 4-nano, replacement customers should be mostly mid-end AI ASIC chip customers and networking customers and automotive processor customers and connectivity products and some lower cost version of AI product. There's no sudden reduction in overall capacity in 3-nano. It's actually just more like cascading. 4-nano and 5-nano is moving to 3-nano and 3-nano is moving to 2-nano or A16 and then moving to A14. It's more like cascading. There's no vacancy in between, but all the nodes like 7-nano, it is actually getting more impacted. There's much less customers.

Client [00:44:35]: Yes, 7-nano and 10-nano were never big anyway.

00:44:35] TSMC said 5-nano will shrink over time as customers move to 3-nano. What do you think?

Expert [00:44:51]: Also, there's some surprising number of customers, especially the networking for AI can jump several nodes because actually, the decision is based on power efficiency vs the cost. If the power efficiency improvement and some speed improvement justify higher cost, then they can jump to several nodes. Those kind of things as long as it actually justify the higher cost for the improvement in the power consumption and performance. Actually, I also have some interesting dataset. That's also included in your talking point. The list of wafer price and wafer cost for 2-nano and 3-nano for Samsung and TSMC.

There's a big difference actually. It's interesting because just looking at the TSMC starting from 3-nano, overall wafer cost for 3-nano for now… Wafer cost means the cost for producing one wafer. That's the wafer cost. That's actually more like production cost for one wafer for 3-nano. That's estimated to be roughly about USD 13,000 per wafer. That's the wafer cost, but the real selling price nowadays is ranging from USD 20,000-22,000. It is a lot higher than the wafer cost. That's why they are having high profit margin. Wafer cost is much lower than Samsung because their yield is quite higher because just wafer cost for Samsung for 3-nano is roughly about USD 20,000 per wafer. That's way higher than TSMC, but the selling price, the Samsung is making a lot of discount. The discount, it's actually known to be between 20-30% discount compared to TSMC.

Client [00:47:56]: Is this between USD 15,000 and 16,000?

Expert [00:47:59]: It's actually 30% discount from TSMC actually makes USD 14,000 and 20% discount is making USD 16,000 because TSMC is USD 20,000. That's a minimum. Actually, TSMC is ranging from USD 20,000-22,000. Samsung is making 20-30% discount, so the real selling price is USD 14,000-16,000 per wafer. It's a big loss of money, about 30%.

Client [00:48:39]: It's 3-nano, so it still doesn't have any customers, right?

Expert [00:48:43]: I also have a 2-nano. TSMC, their production cost, that's actually assumption that the yield is somewhere between 75-80%. That's what most of the media report is saying. TSMC's 2-nano has already reached to 60% according to the public report when they started the production. When they finished the internal qualification, they were at 60%. Now it's actually passing the 70% and approaching to 80% these days. Based on that assumption of yield, the production cost for one wafer is USD 18,000 per wafer for 2-nano, but real selling price is currently higher than USD 30,000, so higher than USD 30,000. It's at least 70% profit margin. Samsung is a little bit better in the 2-nano than 3-nano, but still their yield is assumed to be between 50-60%.

The production cost for one wafer is estimated to be USD 24,000 per wafer. It's actually more than 20% lower yield. USD 24,000 is their wafer cost, but the real selling price, the discount rate is even higher now than 3-nano. It looks like Samsung is quite desperate to attract the customer because Samsung is considering 2-nano as a turning point of the business. They're very desperate just making 2-nano as more like turning point and starting of recovery and a credibility reset. They might look like they're more aggressive in discounting those prices. Still losing money, but the amount of percentage of loss is actually lower, smaller than 3-nano.

00:53:12] What are Intel's plans for 14A?

Expert [00:53:22]: Yes. Intel is thinking 14 Angstrom is like a Samsung 2-nano. Intel is considering 14 Angstrom as a turning point. 18 Angstrom is still there's almost no external customers. Intel is saying that, "Oh, this is just a practice," something like that. Intel is thinking 14 Angstrom is a major node that's starting some business with the external customers. The top management is thinking that they should secure some major customers from 14 Angstrom. I think their CEO actually publicly said that if they fail to have enough external customer from their 14 Angstrom product, they were considering to significantly decrease or even stop the business.

Client [00:54:32]: Yes. He's negotiating very publicly with a variety of stakeholders.

Expert [00:54:38]: Actually, Intel's status is still unclear and not very promising in terms of business as Samsung, but still have some success. One of the big success is they actually had a deal with AWS. That's AWS AI fabric chip that's actually using Intel's 14A process. That's the first case of committed and commercial design with volume and some high-volume manufacturing case. That's the first case from major customers.

Client [00:55:18]: Is that like a proprietary networking chip?

Expert [00:55:21]: Yes. That's the strongest Intel external wafer commitment so far, but that's still just one because there's no other yet. There are also some public reports that says Microsoft stated that it selected the chip design that it plans to produce on 18 Angstrom, but that's a plan that they said. It's actually more advanced than just simple evaluation, but it's not publicly committed to high-volume production yet. It's still not clear. There's some announcement…

Client [00:56:03]: Microsoft has several issues with its own chips. How do you view that?

Expert [00:56:07]: Yes. There's also some announcement of US defence customers, US government, but it's not really manufacturing. It's more like validate some secure manufacturing design flow. It's using test chip and some prototype and some qualification process. It's not really some meaningful scale volume production. Intel has actually already distributed the PDK and other things for 14 Angstrom already because Intel said that they're going to finish the development of 14 Angstrom process by end of next year and they're going to start to test run from some time around the end of next year. That's actually earlier than TSMC in the timeline. They're always making earlier than TSMC, but they fail. Major production will start in 2028. That's almost the same timeline. TSMC is also planning to start 14 Angstrom. I think that's the later part maybe, I think it's probably Q4 in 2028.

Client [00:57:34]: Yes. It is trying to make that, right?

Expert [00:57:38]: Samsung also plans to start the production of 1.4-nano originally from 2027, but they actually delayed those timeline to 2029. It looks like the overall internal qualification and wafer start for 1.4-nano for 2-nano Samsung. I think it starts by end of 2028 or early 2029, but actually roughly about same timeline for those three customers.

Client [00:58:31]: 1.4-nano for everyone is a second gate-all-around node. Is everyone roughly on the same page?

Expert [00:58:39]: Yes. Definitely for Intel and Samsung. Let me see. Samsung employ backside power delivery from SF2Z, so that's the last generation of the 2-nano family. 1.4-nano definitely have backside power delivery.

00:59:22] Where are DRAM-base dies being made right now? Does Samsung make its own, while TSMC makes SK and Micron?

Expert [00:59:35]: Until HBM3E, those are all made internally in the DRAM fab until HBM3E.

Client [00:59:58]: Is it a 14nm or 13nm process?

Expert [01:00:03]: I think it's actually higher than that because 14 Angstrom [sic] is already FinFET, but I'm definitely sure that it's not FinFET. It should be high teens, like 18-nano or something. I know it's not FinFET-based.

Client [01:00:28]: It's still planar. Are they moving to an HBM4E base die?

Expert [01:00:31]: From HBM4, the role of base die is significantly increased because the role of base die is actually just minimise the errors in operation. It's actually more operation of controlling the NAND. That also is actually just making some kind of use for improving overall speed and power consumption as well. That was not really significantly important until HBM3E because those requirements for the ping speed and power consumption can actually be achieved even without anymore aggressive redesign or aggressive adoption of leading-edge process, but from HBM4, overall requirement is actually just getting increased so that those function and role of base die in HBM4 is significantly more important.

Client [01:01:53]: Will those be on 4-nano, 5-nano?

Expert [01:01:58]: Actually, those three companies, three DRAM process is quite different for that. That actually makes the overall success or overall landscape of competitive relationship because SK Hynix, they actually just made strategic partnership with TSMC. They just let the TSMC to manufacture their base die for HBM4. TSMC is using 12-nano mostly, but they also said that some specific customers, some specific purpose, they also use some part of 5-nano. Majorly using 12-nano, but some part is 5-nano. That's what they said. Micron, the top management made a decision. It actually turned out to be a misjudgement, but they made a decision to just continue using their own DRAM process for their base die in HBM4, but that just turned out to be a big mistake because what is actually just happening was that initially, the speed requirement, which is called ping speed, the ping speed requirement for HBM4, that was determined by JEDEC.