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2026.09.30 | TB | TSM | TSMC 3Q26 Channel Check

原标题：TSMC – Q3 2026 Channel Check – Advanced Process Capacity Expansion Progress & Utilisation Rate Outlook (Conducted in Mandarin)

#semis

Third Bridge · 2026-09-30

Analyst-led • 28 Sep 2026

Companies: 2330 TW, AAPL US, ASML NL, NVDA US

Expert Independent Consultant

Charlie Peng (CP) — Third Bridge Sector Analyst

Agenda

Key Insights

Introduction

CP: Hello and welcome to Third Bridge’s Interview entitled TSMC – Q3 2026 Channel Check – Advanced Process Capacity Expansion Progress & Utilisation Rate Outlook (Conducted in Mandarin). My name is Charlie Peng, Third Bridge’s Sector Analyst, and I will be facilitating today’s Interview. We are very pleased to have [Expert], who is a former President at Komico Technology Taiwan Ltd, with us today.

Expert], before we start today’s Interview, please state if you agree or disagree to the following statement: You understand the definition of material non-public information and agree not to disclose any such information, or any other information which is confidential, during this Interview.

Expert [00:00:41]: I agree.

Questions

00:00:46] How are TSMC's capacity utilisation and capacity changes for advanced processes in Q3, including 7nm, 5nm, 3nm or the latest 2nm?

Expert [00:01:10]: Capacity expansion for advanced processes is continuing, such as 7nm, 5nm, 3nm and 2nm. The most aggressive expansion is in 3nm. Overall capacity for 7nm has also increased. This is because it allocates some back-end processes of 3nm or 5nm to run on 7nm. Specifically, at TSMC's Fab 15B, some 3nm and 5nm metal processes are run on 7nm. For 7nm capacity, it did not reach 100% when running only 7nm previously. Now it is practically at 100%. We do not even need to mention 3nm and 5nm because they are at full capacity. As for 2nm, it is in a state of continuous expansion and is always at 100%. Mature processes are also running at full capacity, based on my understanding. The average is about 90%.

CP [00:02:37]: Compared to three months ago, capacity utilisation for both advanced processes below 7nm and mature processes has seen a significant increase. Is this understanding correct?

Expert [00:02:49]: That’s right. TSMC is very busy now.

CP [00:02:58]: Apple’s new iPhone models were launched two weeks ago, and Rubin has also increased production capacity from July to August. If we only look at 3nm and below processes, will their capacity utilisation rate continue to increase in H2 this year or even H1 next year? Could it exceed 100% or just remain fully loaded? What do you think will happen?

Expert [00:03:21]: It is staying fully loaded while simultaneously expanding. Its current capacity is simply nowhere near enough. Demand is vastly outstripping supply because AI chips are constantly taping out. From what I understand, 3nm is particularly tight right now. It is basically always in expansion.

00:03:56] There has been a lot of news lately about TSMC's pricing trends. It may have already raised prices by 10-15% in H1. Recent reports also suggest another 5-10% hike is coming in 2027. Have you observed this trend? Are these recent price increases already reflected in end products?

Expert [00:04:20]: The price hikes I am aware of are mainly targeting advanced processes. From what I gather, it will likely raise prices again in 2027 because supply is falling completely short of demand. This will again focus on advanced nodes. I am not entirely sure if this is trickling down to consumer products yet. Apple's phones are incredibly expensive now, so I imagine it is being priced in to some degree. I think TSMC has the leverage to raise prices. The 2026 price hikes went through very smoothly. I doubt anyone will dare say no to another 5-10% increase in 2027. AI demand is flooding in, and the price hikes are not exactly outrageous. We are not talking about 20-30% spikes. A 5-10% bump fairly reflects its current cost pressures. These include higher labour expenses, US manufacturing costs and the general overhead of international expansion. I think it is quite reasonable, so the price will almost certainly go up.

CP [00:05:56]: TSMC seems to be raising prices a bit more frequently in recent quarters. For instance, recent news showed that certain wafer materials have been seeing continuous price hikes of 15% to 30%.

Expert [00:06:11]: Yes, but its price increases are justified. Major wafer suppliers such as GlobalWafers and Japan's Shin-Etsu are also raising their prices. TSMC's underlying costs are naturally going up. I think its price adjustments make perfect sense. You mentioned the frequent price hikes, but it is really just passing on the rising costs across its supply chain.

CP [00:06:45]: You feel TSMC generally will not face much pushback when raising prices?

Expert [00:06:49]: Exactly, clients will basically accept the higher prices. Negotiating with TSMC is understandably difficult. However, they are slightly more open now given the overall supply chain situation. TSMC is showing a bit more flexibility. It used to play hardball during negotiations, but it is more open now. To put it bluntly, capacity is simply insufficient everywhere. It also wants support for its international operations, so it currently holds more bargaining chips in the supply chain. Prices are going up upstream, so it passes those costs onto its customers. Ultimately, I believe this will inevitably push up the prices of end products. This might explain why US inflation is proving stubborn. That is obviously tied to oil prices and other macroeconomic factors, but general baseline costs are definitely creeping up.

CP [00:07:52]: Major Japanese equipment manufacturers such as TEL and Disco have hinted at price increases. Will they start passing these higher equipment costs onto TSMC in H2?

Expert [00:08:06]: That’s right. This applies to all equipment suppliers. I do not have direct confirmation, but my understanding is that they are all preparing to make a move. They need to capitalise on the current market timing. As I mentioned, this pressure originates upstream. The costs for internal components such as PC boards are all going up.

00:08:35] Discussions about price hikes have dragged on for years. The increases in 2025 and 2026 feel particularly rapid. Are any specific factors accelerating this trend?

Expert [00:08:50]: The AI boom has triggered a massive demand shock, and supply simply cannot keep pace. It is that straightforward. This is a typical supply and demand scenario. For example, Apple used to be TSMC's dominant customer, giving Apple immense bargaining power. When TSMC wanted to raise prices across the board, the biggest client would block it, and others would follow suit. Now, AI is creating a crowding-out effect. Orders from companies such as Nvidia, AMD and various ASIC designers are flooding in at a terrifying rate. This has effectively created a seller's market. Under these conditions, it makes perfect business sense to raise prices now. If not now, then when? The scale of AI end-market demand and hyperscaler orders is truly unprecedented. We have never seen anything like this before.

00:10:29] You mentioned earlier that alongside 5nm and 3nm, TSMC's 7nm capacity is also packed. The market seems to be paying less attention to 7nm right now. How do you view the capacity expansion for 7nm?

Expert [00:10:51]: When I discuss 7nm, I am primarily referring to TSMC's Fab 15B. TSMC's Fab 15B was underutilised for a long time. It was hovering around 70% utilisation. What is 7nm historically used for? It was heavily reliant on crypto mining chips and mobile processors. That specific demand is no longer as robust. Throughout periods such as 2025, its full-year utilisation hovered stubbornly around 70-75%. However, it has been steadily climbing since the start of this year and is now above 90%. Total capacity for 6nm and 7nm at 15B is 150,000 wafers. It is actually closer to 160,000 wafers. It is currently running at 150,000 wafers, whereas it was only churning out around 100,000 to 110,000 wafers this time last year.

It has some back-end metal processes originally designed for the 3nm, 4nm and 5nm nodes. These processes are normally handled at Fab 18. The number of chambers in No. 18 Factory is not enough because there are many processes for metal materials, which take a long time to process from the middle-end to back-end. Facing a chamber shortage, it is moving some wafers over to Fab 15B. Those semiconductor reaction chambers can be shared. Certain metal chambers on equipment from Applied Materials and Lam Research are compatible across nodes. Therefore, it is reallocating some overflow work from Fab 18 to Fab 15B.

It is not that end demand for 6nm and 7nm has miraculously recovered. It has simply shifted about 20% of its capacity, boosting utilisation by that same margin. For example, why did it jump from 70% to 90% or 95%? That extra 20% or so is actually processing back-end steps for 3nm, 4nm and 5nm wafers. It repurposed those chambers for back-end processing. It is not running native 6nm and 7nm wafers. It is processing 3nm, 4nm and 5nm wafers. The chambers dedicated to 3nm, 4nm and 5nm are completely maxed out.

CP [00:14:18]: When we evaluate 3nm or 7nm volumes, are front-end and back-end processes counted together or tracked separately?

Expert [00:14:27]: They are counted together as total wafer output volume. The volume processed at 15B is essentially included within the total figure. If I say Fab 18 is producing 150,000 wafers for 3nm, all of the stages are included. It is not counted twice.

CP [00:14:50]: You noted that the 7nm fabs are seeing higher utilisation rates, but this is not driven by core 7nm demand. How is the actual underlying demand for 7nm right now?

Expert [00:15:02]: It remains fairly flat. There has been no explosive growth there.

00:15:12] Recent reports suggest TSMC's 3nm capacity might hit 180,000 wafers by year-end, targeting 210,000 wafers next year. That sounds slightly lower than the 200,000 wafers you estimated last time. Has the 3nm expansion speed picked up compared to three months ago? Given the fully loaded utilisation, what is your take on the pace of expansion?

Expert [00:15:50]: I still think 200,000 wafers is the more realistic figure. Regarding the 180,000 estimate, it is already late September now. The 3nm output at Fab 18B has already crossed 160,000 wafers. Saying it will hit 200,000 wafers by year-end is quite accurate. It should land right around that number.

CP [00:16:33]: Is it about 180,000-200,000?

Expert [00:16:36]: Yes, adding another 20,000 to 30,000 wafers between now and December sounds like no problem to me. I would argue 180,000 is an underestimation. I believe it will reach 200,000. The 210,000 figure you quoted is for next year. A target of 210,000 for next year is a little too conservative. I expect them to revise that upward. The exact timing next year is the crucial factor.

CP [00:17:35]: There is a lot of mixed messaging right now. Some believe new capacity can be unlocked in H2. If they begin ramping up, 210,000 wafers actually seems unusually low. What are your projections?

Expert [00:17:51]: Let me double-check the phase breakdown for Fab 18B.

CP [00:17:54]: Fab 18B should have eight phases operational right now. Phase 9 probably will not come online until next year.

Expert [00:18:02]: Correct. Phase 9 is not ready yet. Each phase handles 25,000 wafers. Multiplying 25,000 by eight is 200,000 wafers. That assumes all eight phases are running at full tilt. I am confident it will do everything in its power to keep them fully operational. The margins on this are simply too lucrative. I think it will try its best to make it run at full capacity because this is very profitable.

CP [00:18:29]: The 25,000 wafers you mentioned is an average benchmark. Given the intense recent demand, could they reduce downtime to push the capacity rate slightly higher? That is definitely a possibility, right?

Expert [00:18:41]: Yes, it absolutely has the technical capability to do that. Furthermore, as I mentioned, shifting some back-end processing to Fab 15B makes reaching 200,000 wafers entirely achievable. P9 is not operational yet. It will come online next year and add another 25,000 wafers.

CP [00:19:10]: You previously noted that it could hit 30,000 wafers under maximum load conditions.

Expert [00:19:14]: Yes, but that's when the capacity is beyond normal limits. It can hit 30,000, but it leaves zero margin for error across the board.

CP [00:19:29]: Therefore, we cannot realistically project 240,000 wafers. That would be far too aggressive.

Expert [00:19:32]: It will not push things that aggressively. I think TSMC can comfortably deliver 25,000-27,000 wafers per phase. I have seen it hit 30,000, but it is a rare occurrence.

CP [00:19:57]: To sum up, looking at Fab 18's P1 through P8 by year-end, each fab yields roughly 25,000 wafers. Eight fabs average out to nearly 200,000 wafers. This logic holds up well, right?

Expert [00:20:11]: The logic is sound. Based on what I know about their current operations, they are grinding incredibly hard to squeeze out every drop of capacity daily. I think having all eight phases running fully by year-end is a very reasonable expectation. The crucial takeaway is that it has not hit any major bottlenecks. It is simply replicating proven setups, making the expansion process highly stable. The only real risk factor is equipment delivery. I have not seen any alarming delays on the equipment front, though.

00:21:02] Recent news frequently highlights TSMC accelerating its fab expansion. However, it sounds like every existing fab is already maxed out. Where exactly is this accelerated expansion happening? Do you think it is speeding up construction? For instance, could it advance P9 to start ramping up in H1 next year, or pull forward the P10 timeline? Are these scenarios realistic?

Expert [00:21:27]: There are many explanations for accelerating expansion. It could mean project schedules are moving up, or equipment is being installed faster. It might also refer to optimising manpower and fab floor space. For example, migrating back-end processes to Fab 15 is a form of acceleration. There is also the 3nm project in Japan and the 3nm facility in the US. Those overseas sites have far more room to accelerate. I honestly do not know how it could speed things up any further in Taiwan. Operations here are already stretched to the absolute limit.

CP [00:22:13]: P9 might not hit mass production until H2 next year, and P10 will follow even later. Is it possible to speed up the construction of fabs? Could it partner more closely with local Taiwanese contractors to fast-track things, or is it hitting fundamental physical limits?

Expert [00:22:29]: The supply chain is full now. Everyone bends over backwards when TSMC makes a request, but there are physical limits. As for P9, I have not heard any credible chatter about accelerating its timeline. It appears to be tracking to the original schedule.

CP [00:22:49]: I also have not picked up any signals about P9 or P10 accelerating. This is likely tied to broader supply chain constraints, right?

Expert [00:22:57]: That’s right. There are simply too many fabs being built concurrently right now. The true bottleneck for these advanced nodes is not front-end wafer fabrication. The real choke point is back-end packaging.

CP [00:23:24]: When you mention back-end processes here, are you referring to the back-end metal steps at Fab 15 or advanced back-end packaging?

Expert [00:23:35]: I am referring to advanced packaging technologies such as CoWoS.

CP [00:23:37]: Overall, the potential to accelerate 3nm in Taiwan is severely limited. P9 and P10 are locked into their timelines. That means we have to look to the Japanese and US fabs you mentioned, right?

Expert [00:23:53]: Yes. If you want to find spare capacity to accelerate, there is much more runway over there. This is particularly true for the US. I think TSMC's operational proficiency in the US has improved significantly. Early reports suggested the US schedules were overly conservative. I strongly believe those timelines will be pulled forward, just as I predicted earlier.

CP [00:24:28]: The situation in Taiwan remains largely unchanged from three months ago, but Japan and the US offer substantial upside, correct?

Expert [00:24:36]: Yes, Japan has not officially ruled anything out. Regarding the US, my intel suggests many of their active projects are moving at a rapid clip. They are heavily benchmarking against Fab 18 over here, specifically Fab 18B. This is a standard prerequisite for preparing mass production at the P2 3nm fab. That process is currently in full swing and progressing very aggressively.

CP [00:25:22]: Let’s talk about Taiwan fabs a little more. Taiwan sits at 200,000 wafers, driven by eight fabs doing 25,000 wafers each. Fab 9 will bring another 25,000 wafers online next year. P10 will follow in 2028. There are currently no firm updates on P11 and P12.

Expert [00:25:41]: I have not seen any movement on P11 and P12 either. P9 is definitely happening. My outlook remains largely consistent with my previous forecasts.

00:25:55] TSMC announced it will invest another USD 100bn in the US. That is a staggering figure. There is a flurry of news surrounding the US fabs right now. Current estimates point to P2 reaching mass production in H2 next year. Are you seeing any accelerated progress at the US sites, either for P1 or P2?

Expert [00:26:21]: P1 is effectively stabilised now. As for P2, based on my experience and what I am currently observing, many workstreams over there are genuinely accelerating. The aggressive benchmarking I mentioned proves they are eager to move the schedule up. They are pushing very hard to advance the timeline. The official corporate line still targets mass production for H2, correct?

CP [00:26:55]: Yes, H2 next year. However, is there a chance they could hit mass production in H1 this year, or perhaps Q1 next year?

Expert [00:27:02]: I think that it can achieve high-volume mass production in H1. They are currently installing equipment and running pilot lines. The extensive benchmarking I mentioned only happens during pilot phases. If you ask me, that specific timeline will be pulled forward. I would not be the least bit surprised if they beat their official guidance by one or two quarters. A massive chunk of their baseline demand originates from the US anyway.

00:27:50] Given that TSMC's US fab is already moving equipment in, what levers can it pull to speed things up? Would it squeeze the supply chain or force a faster ramp-up? A full ramp-up usually takes two to three quarters. What is your perspective?

Expert [00:28:02]: When the machine comes in, the installation part can be accelerated, and then the verification and inspection parts can also be accelerated. It needs to be benchmarked against 18B, which can be accelerated. I haven’t heard of any delay in the delivery of equipment so far, but it is possible to speed up. Furthermore, TSMC is incredibly adept at optimising the entire lifecycle from equipment delivery and installation to pilot runs and risk production. It can aggressively compress this timeline. The ramp-up trajectory can steepen dramatically because it has already done all this at Fab 18. The biggest challenge in the US is human capital. It is always a personnel issue. That is exactly why it has relocated so many engineers to the US recently.

CP [00:29:15]: Assuming they ramp up capacity on a very steep curve, the US P2 fab should hit full production before the end of next year. That would secure the 25,000 wafers we discussed, right?

Expert [00:29:29]: Under an optimistic scenario, it has a solid chance if it kicks things off in Q1 or Q2 of 2027. The caveat is that it needs to enter mass production before Q1 or early Q2 to have a shot at running 20,000 to 25,000 wafers.

CP [00:30:13]: Does it hinge entirely on whether the supply chain can execute flawlessly right now?

Expert [00:30:19]: That’s right. If you ask for my honest opinion, I think the odds of P2 fully ramping up by next year are very favourable. I see a very high probability that P2 is running at maximum capacity by the end of next year. That has clearly become a top priority for TSMC.

00:30:38] TSMC's US P3 fab just broke ground in Q2 this year. According to standard fab construction timelines, such as the two and a half to three years required for P2, P3 might not reach mass production until 2028 or 2029. Based on historical trends, how much can milestones such as equipment move-in be pulled forward?

Expert [00:31:00]: We need to look at TSMC's learning curve. P2 is going to be faster than P1, so it is perfectly logical to expect P3 to outpace P2. The learning curve shrinks with every iteration. It will extract valuable lessons from P2 and apply them directly to P3, boosting overall speed. Let me verify the current official schedule for P3.

CP [00:31:37]: The official guidance says before 2030.

Expert [00:31:40]: That is an incredibly conservative estimate. It claims 2030, but we are sitting in 2026 right now. It simply will not take that long. If I had to wager a guess, I would say late 2028 is highly feasible.

CP [00:32:08]: When you say late 2028, are you forecasting risk production or full mass production? Risk production and equipment move-in usually happen slightly ahead of schedule, right?

Expert [00:32:17]: Risk production. The current official line is 2030, right?

CP [00:32:22]: That’s right.

Expert [00:32:23]: I think it can be fully developed in 2029.

CP [00:32:33]: If mass production hits in 2029, risk production normally precedes it by a few quarters, placing move-in even earlier. Could it move even faster? Might we see major equipment activity in H2 of 2027 or H1 of 2028?

Expert [00:32:49]: It's breaking ground in 2026, construction in 2027, followed by equipment installation. I think late 2027 or early 2028 is possible. However, that is a very aggressive timeline that assumes the physical construction phase all goes smoothly.

CP [00:33:08]: Judging by current volumes, it is very hard to spot any concrete evidence of accelerated progress for P3 right now, right?

Expert [00:33:17]: Yes, we are firmly in the realm of educated guesswork at this stage. It is impossible to predict the future situation.

CP [00:33:28]: Generally speaking, the broader industry expects TSMC to beat its own timelines, right?

Expert [00:33:32]: The initial roadmap it publishes is always beaten later. If TSMC says 2030, you should automatically shave at least a year off that estimate.

CP [00:33:46]: That seems to be the consensus view across the market. Deduct at least one year?

Expert [00:33:49]: Yes, that has always been its playbook. It is very similar to how Nvidia manages earnings expectations.

00:33:57] Official channels state TSMC's German fab will commence production in 2027, with the second Japanese fab targeting 2028. Given the intense current demand, fully maxed-out Taiwanese fabs, and a lack of physical space in the US, have you picked up any supply chain chatter? Will TSMC fast-track equipment move-in or finalise mass production dates for its overseas 3nm fabs earlier than expected?

Expert [00:34:27]: The German facility is entirely disconnected from advanced processes. Its roadmap focuses strictly on mature nodes such as 22nm and 28nm. That strategy remains unchanged, meaning Europe will not see advanced manufacturing. The Japanese fabs are a topic of active discussion. The P2 facility in Kumamoto is officially announced, targeting 15,000 wafers and mass production by 2028. That is the established public information. From what I hear regarding JASM, it is struggling with a severe manpower shortage. TSMC is routing its top talent to the US first. This personnel allocation is exactly why I am so bullish on the US 3nm timeline. I know it is executing that US strategy with extreme aggression. This might be driven by client proximity, US government or other factors. However, while there are discussions and even official announcements regarding Japan, I am not seeing aggressive manpower planning for that region. I strongly suspect it simply lacks the personnel to properly staff three distinct sites while simultaneously managing the massive 3nm expansion in Taiwan.

00:36:36] We noted earlier that the US hosts major clients such as Apple and key AI players. Japan skews heavily towards automotive and mature processes. That suggests TSMC lacks a compelling business case to accelerate 3nm in Japan. Has that dynamic shifted?

Expert [00:36:51]: I consider that a pivotal factor. Projects located near core customers naturally command higher priority. I am highly sceptical about deploying advanced nodes in Japan. Establishing a global manufacturing footprint looks good on paper, but you have to question the actual return on investment. Why not just expand domestically in Taiwan? Building in Japan makes little sense when expanding in Taiwan is significantly cheaper.

CP [00:37:30]: There is a persistent narrative that expansion in Japan moves rapidly because the local government is highly cooperative.

Expert [00:37:39]: The Taiwanese government is equally cooperative. TSMC is the heavyweight here. Nobody dares deny it anything it needs.

CP [00:37:50]: Do you still believe that even with TSMC operating at maximum capacity, it will continue to prioritise Taiwan and its US facilities? The US fabs likely offer more strategic upside, right?

Expert [00:38:01]: The US fabs represent direct proximity to core customers. That is a hard commercial reality, compounded by pressure from the US government. You tell me that the Japanese government being supportive, demanding 3nm tech and a massive resource transfer. But what does that support actually look like? It did not offer a massive financial subsidy, and the local customer base for advanced nodes is virtually nonexistent.

00:38:30] Current reports indicate TSMC's 2nm capacity will hit 90,000 wafers by year-end and scale to 110,000 wafers next year. The 90,000 figure aligns closely with our previous discussions. However, I personally feel scaling to only 110,000 wafers next year represents a lacklustre increase. What is your assessment? Has the 2nm rollout accelerated compared to three months ago? Are there any notable shifts in next year's roadmap?

Expert [00:39:12]: I based those previous estimates on its actual output numbers and internal projections at the time. When we discuss 2nm, we are specifically talking about Fab 20 and Fab 22. Fab 20 has two phases, while Fab 22 has four. As of September, Fab 22 is outputting 60,000 wafers. Fab 20 contributes less because it functions as the mother fab, outputting roughly 20,000 wafers. That already puts it at 80,000. It might be marginally under 20,000, so we can adjust the math slightly. We are in Q3 of 2026, and it is already sitting at 80,000. Crossing 100,000 by year-end is absolutely achievable. It may well exceed that mark.

00:41:01] Currently, P1 and P2 at Fab 20 should be running fully loaded. You mentioned these two phases act as the mother fab. Under normal conditions, a single standard fab should output between 25,000 and 30,000 wafers, correct?

Expert [00:41:15]: Yes, but Fab 20's output is structurally lower. It is consistently lower because it frequently diverts equipment for R&D and process development. It is not designed as a pure mass production facility, pulling its overall numbers down. The figures for Fab 20 often look slightly strange because it is not a production fab. When estimating true mass production fabs in the 25,000-30,000 range, you should be looking at facilities such as Fab 22. Fab 20 is a unique exception.

CP [00:41:53]: For Fab 22, Phase 1 and Phase 2 should be in mass production now, while Phase 3 is undergoing risk production. Is that accurate?

Expert [00:41:59]: Yes, the latest data I saw showed output exceeding 60,000 wafers.

CP [00:42:04]: Does that 60,000-plus figure include output from Phase 3?

Expert [00:42:08]: It includes Phase 3. Phase 1 and Phase 2 are completely full, accounting for 50,000 wafers. Phase 3 is actively ramping up, pushing the total to 65,000. Phase 4 will be operational by year-end. If you suggest Fab 22 could output 80,000 wafers by year-end, I would not be surprised in the slightest. In fact, I suspect that might serve as the bare minimum baseline.

CP [00:42:36]: Sorry, we should probably recalibrate this timeline slightly. Previously, Phase 3 was expected to begin its ramp-up in Q3 this year. The original guidance suggested P4 would only start ramping next year. Are you saying P4 will actually generate volume this year?

Expert [00:42:53]: It is only late September. We still have three full months left in the year. The timeline is definitely moving faster than when we last discussed it.

CP [00:43:04]: P3 will generate volume, but it likely will not hit its full 25,000 capacity this year. It cannot ramp up quite that fast. However, P4 could reach full capacity by H1 next year. Is this reading correct?

Expert [00:43:14]: It absolutely will, and it might even surpass that target. The schedule could be pulled forward even further.

CP [00:43:23]: Just doing some back-of-the-envelope math, the four phases at Fab 22 alone will unequivocally be fully loaded by the end of next year. That guarantees at least 100,000 wafers. Factoring in the two phases from Fab 20, which add roughly 20,000 wafers, reaching 120,000 wafers by the end of next year seems effortless, right?

Expert [00:43:37]: Sure, absolutely no problem. The demand for 2nm is staggering.

00:43:48] Given that, P3 is definitely receiving equipment and prepping to ramp. P4 is also in the move-in phase. Has there been any official communication regarding P5?

Expert [00:44:10]: I have not seen much solid intelligence regarding P5 yet.

CP [00:44:54]: It is probably still just hearsay. Based on this conversation, the potential to accelerate 2nm actually seems far greater than 3nm, right?

Expert [00:45:05]: I believe so. From what I can see, the initial 2nm rollout is demonstrably faster than the early days of 3nm. I am unsure if the rapid progress at Fab 22 relates to better staffing, but its overall posture is incredibly aggressive.

CP [00:45:33]: Regarding these faster timelines, 2nm represents a major architectural transition, making the process significantly different. Where exactly are they finding these efficiencies? Is it in process engineering, assembly line optimisation, or tighter supply chain integration? Which component is driving the acceleration?

Expert [00:45:47]: I attribute it entirely to its internal engineering. I do not think the supply chain is the primary driver. It comes down to TSMC's internal process development and its unmatched ability to rapidly copy exact tooling setups. The production lines are running flawlessly. I have not heard a whisper about major technical hiccups. The entire ramp-up is exceptionally smooth. This efficiency might also stem from handling fewer distinct products at this early stage.

00:46:17] Looking ahead to 2028, what levers remain to further expand 2nm capacity? Fab 20 and Fab 22 sound like they will hit a hard ceiling by H1 next year. By 2028, will capacity growth rely entirely on the rumoured Phase 5 or unlocking space at overseas fabs?

Expert [00:46:39]: The US P3 fab will provide some overseas capacity. That satisfies the baseline demand from US clients, but that is the extent of it. Regarding 1.4nm, TSMC has already diverted engineering talent to spearhead that project. It is actively focused on 1.4nm development. However, TSMC is highly adaptable. If 2nm demand remains white-hot, it can easily expand the Kaohsiung site. It has banked land there specifically for future expansion, so physical space is a non-issue. The next major technological bridge is the 1.6nm node. It is already processing some 1.6nm test orders.

CP [00:47:28]: Is 1.6nm capacity bundled into the fabs we just discussed?

Expert [00:47:33]: Yes, it is fully integrated into those roadmaps. We generally do not separate 2nm and 1.6nm in these discussions because they share the same fundamental technological DNA. It is vital to understand that 1.6nm is not 1.4nm. 1.6nm is essentially an optimised 2nm node.

CP [00:47:48]: Recent reports claim Fab 25 was originally slated for mass production in H2 next year, but that timeline might be aggressively pulled forward to April. That represents a massive acceleration. What is your perspective on this?

Expert [00:48:03]: That should be wrong. It must be referring to Fab 20. Fab 25 down in Taichung is nowhere near ready for that.

CP [00:48:19]: You just mentioned that P4 will definitively hit full production next year. This capacity umbrella also covers the 1.6nm volume, correct?

Expert [00:48:25]: Yes, it will definitely be fully loaded.

CP [00:48:31]: Does mixing 2nm and 1.6nm create any internal capacity allocation bottlenecks?

Expert [00:48:38]: Not really, because I hear the manufacturing processes are remarkably similar. As for the customer breakdown, I tried digging into the exact capacity split between 1.6nm and 2nm. I asked around extensively, and nobody has a definitive answer.

00:49:06] You touched on 1.4nm development accelerating, but Fab 25 obviously cannot output wafers next year. What does the realistic mass production curve look like here? Is 2028 still the most credible target?

Expert [00:49:24]: A more plausible scenario is that Fab 20 might initiate pilot production for the A14 process in Q1 next year. As for Fab 25, the absolute earliest we will see equipment move-in is Q1 or Q2 next year. Hitting risk production and pilot runs by the end of next year would be really impressive. The official corporate roadmap targeting 2028 for mass production remains highly credible. The ultimate timeline depends heavily on end-market adoption and pricing power. If a 1.4nm wafer commands an astronomical premium, resources will pivot sharply in that direction, potentially pulling the timeline forward.

00:50:20] What is the current capacity target for TSMC's 1.4nm Fab 25? Will a fully loaded phase still output the standard 25,000 to 30,000 wafers?

Expert [00:50:33]: Yes, TSMC is always like this. A new facility such as Fab 25 always starts as a basic setup, followed by P1, P2, P3 and P4. Subsequent expansion is dictated entirely by market demand. Look at Fab 18. Each phase was engineered for 25,000 wafers. Fab 18A initially mapped out just four phases for 5nm and 4nm, capping at 100,000 wafers. It typically draws up four phases initially to hedge against demand fluctuations. Then it scales up. Fab 18A eventually bolted on a P7 phase. The industry still does not know what happened to P5 and P6, but it branded it P7 regardless. Functionally, it was just its fifth phase. It just keeps stacking capacity. Fab 25 will follow this exact playbook, starting with P1 through P4.

CP [00:51:38]: Extrapolating from that, maxing out capacity across P1 through P4 probably will not happen until post-2028 or 2029, right?

Expert [00:51:43]: Frankly, that is completely up in the air. I cannot predict what problems it might hit during the ramp-up. Generally speaking, I am slightly cautious about projecting 1.4nm timelines. It represents a radical architectural shift to gate-all-around transistors, which is a major departure from previous nodes. I am unsure if it will hit some problems. According to previous experience, taking a four-phase fab from risk production to full-volume mass production in just over a year has been standard operating procedure.

00:52:22] Given the severely constrained capacity environment, could TSMC repurpose equipment from legacy nodes such as 7nm and 5nm to bolster 3nm output? Since they share the FinFET architecture, would the migration be relatively seamless?

Expert [00:52:40]: I touched on this earlier. Fab 15B originally spun up chambers dedicated to 7nm. Those exact chambers are now processing back-end workloads for the 3nm, 4nm and 5nm generations. "Back-end" specifically means back-end metal deposition. It is already actively executing this strategy. However, this equipment fungibility vanishes when you look at older generations. The hardware simply lacks the necessary cross-compatibility. The hard technological boundary sits roughly between 10nm and 7nm. You absolutely cannot take tooling from 12nm or 16nm lines and use it to process 3nm, 4nm or 5nm wafers. Using etching machines as an example, the technical specifications vary wildly even between different generations of standard NAND flash.

00:53:35] We repeatedly touched on TSMC's severe manpower shortage hamstringing its expansion. Beyond human capital, ASML previously flagged plans to boost EUV [extreme ultraviolet] capacity by 30%. Do you foresee any other looming bottlenecks, such as equipment shortages or stringent environmental assessments? The 2nm project in Longtan was infamously derailed by environmental roadblocks.

Expert [00:54:07]: The Longtan situation was highly anomalous. TSMC usually executes land acquisition and environmental compliance with surgical precision. I suspect the local stakeholders in Longtan deeply regret their opposition now, though back-end facilities will eventually be built there. It is just facing massive delays. In the current political climate, if TSMC decided to bulldoze a golf course tomorrow to build Fab 25, nobody would utter a word of protest. Taiwan's entire economic engine has been supercharged by TSMC and its surrounding ecosystem. Nobody will dare obstruct its expansion plans. Furthermore, TSMC is fiercely committed to its green initiatives. As an industry titan, it enforces incredibly stringent environmental standards internally. It even forces its entire supply chain to adopt rigorous environmental protocols. Therefore, I highly doubt environmental assessments will pose a systemic threat. I firmly believe its single greatest operational risk is human capital. It simply cannot hire fast enough. Every single fab is operating under immense strain, just barely holding the line.

00:55:43] Is recruiting truly that difficult? TSMC operates across numerous technology nodes. Is the talent crunch concentrated entirely in advanced processes, or is it a systemic failure across every production stage?

Expert [00:55:55]: Engineers hired to run mature processes frequently get poached internally to staff the advanced nodes. The teams managing the legacy nodes are left permanently short-staffed and overworked. The advanced fabs are in a perpetual state of headcount deficit because physical expansion is too fast. It is basically short-staffed across the entire company. You now see Western expats and Indian engineers working inside TSMC's Taiwan facilities. It has been forced to look overseas for talent. If you walk the halls of TSMC, you will definitely bump into foreign engineers. While they remain a minority, it proves HR is exploring every possible avenue. Rapid expansion has turned talent acquisition into a monumental headache.

CP [00:57:00]: In fact, it often complains about the power shortage in Taiwan, which may be a sensitive issue.

Expert [00:57:08]: I am not overly concerned about that. Regardless of which political party holds power in the future, the entire establishment understands that supporting TSMC is an absolute economic imperative. Comprehensive power infrastructure planning is firmly in place. These models obviously assume geopolitical stability. If a major conflict erupts between the US and Iran, global markets will naturally suffer. But under normal conditions, TSMC models out these risk factors and builds in massive redundancy. I do not view power constraints as an existential threat. TSMC's primary adversary right now is the talent shortage.

CP [00:58:08]: There is no risk in the equipment, right?

Expert [00:58:11]: I have not heard anything about equipment delays impacting its schedules. It manages its suppliers aggressively. Fab directors routinely fly out to equipment vendors to personally expedite tool deliveries. Why do you think ASML is expanding so aggressively? Their lithography machines cost a fortune and take ages to assemble. ASML would never stockpile that kind of inventory unless its internal demand forecasts completely dwarfed its original projections. This demand is not isolated to TSMC. Samsung, a resurgent Intel and SK Hynix are all aggressively procuring tools. The global appetite for semiconductor equipment is insatiable.

00:59:00] You mentioned the CoWoS [Chip-on-Wafer-on-Substrate] back-end process earlier. The capacity crunch there appears even more acute. Reports suggest TSMC expects CoWoS capacity to experience explosive 70% to 80% growth next year and the year after. Have you noticed a tangible acceleration compared to three months ago? What is your read on the packaging market?

Expert [00:59:20]: The growth will be explosive because current capacity is woefully inadequate. I expect continuous, massive investment here because advanced packaging has become the primary industry bottleneck. This is heavily driven by AI demand. Nobody forecasted that downstream demand would scale to this magnitude. Consequently, it simply did not build out the necessary back-end packaging infrastructure. Once back-end operations are up and running, the margin for error is slightly more forgiving than the front-end wafer fabrication. It already suffered through a brutal learning curve, dealing with and resolving numerous technical gremlins. Operations will run much smoother going forward because it has already encountered and fixed the major systemic issues. The subsequent learning curve will steepen significantly.

01:00:16] Looking ahead, what specific metrics or milestones will you be monitoring most closely? Are you watching expansion timelines or specific fabs? Where should we focus our attention?

Expert [01:00:30]: Keep a close eye on its revenue distribution. For TSMC, the narrative is entirely dictated by advanced processes. Over the next 12 months, the dominant storyline will be the aggressive capacity expansion for 2nm and 3nm. The 3nm node is rapidly evolving into a cash cow. As for 2nm, I am confident it will soon become a foundational pillar for both top-line revenue and bottom-line profit.

CP [01:01:25]: Thanks again to [Expert] for their input today. This now concludes our meeting. Goodbye.