2026.10.06 | Substack | Memory | Next Memory Race Beyond Scaling

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Where the conversation began

Does a lead in HBM translate into a lead in the next generation of memory technology? This conversation made me reconsider that question.

The expert I spoke with develops next generation DRAM processes at SK hynix’s future technology research institute. We began with 3D DRAM, where the cell structure itself is built in multiple layers, then moved to fabricating cells and peripheral circuits separately and bonding them together, HBM manufacturing and customer support, and the role memory companies want to play in AI systems.

What stood out was that the basis of competition differed by technology. In 3D DRAM, fabricating structures laterally inside the stack was closely tied to identifying which internal layer had a problem. With cell and peripheral circuit separation, increasing cell density and improving peripheral circuit performance had to be considered separately.

The expert expressed confidence in the company’s collaborative culture and customer support, while also discussing the limitations of a strategy focused on scaling and the difficulties of new bonding technologies. This report includes not just those conclusions, but the reasoning and practical examples behind them.

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Key takeaways

01 | 3D DRAM faces bottlenecks in both fabrication and validation. Alongside the difficulty of lateral etching and film formation, the speed of detecting internal defects constrains how quickly the next process conditions can be determined.

02 | Separating cells and peripheral circuits changes the basis of competition. Freeing up cell area and developing peripheral circuits independently creates performance and cost options beyond moving to a smaller node.

03 | Start by distinguishing what is being bonded. Bonding cell and peripheral circuit wafers and stacking individual dies for HBM begin from different foundations and face different mass production challenges.

04 | AI memory strategy depends on design, process, and collaboration capabilities. Proposing a memory tier, designing it, and connecting it to other processes or companies are tasks that have to be prepared together.

Editorial note

This is a thematic edit of the original interview, not a verbatim transcript. Questions and answers have been edited for clarity, and related remarks have been connected. The expert’s answers reflect personal views at the time of the interview and do not represent the company’s official position. Background beyond the transcript appears separately, with sources, under ‘Technical background, Editor’s supplement.’ ‘Damnang’s interpretation’ represents the editor’s assessment. Generative AI was used to assist with wording and editing.

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01. What does 3D DRAM change?

Damnang: Could you start by introducing your work?

Expert: I work in process development at SK hynix’s future technology research institute, where I study next generation processes such as 3D DRAM. To understand this technology, it helps to start with what is becoming difficult in conventional DRAM.

Conventional DRAM has evolved by making capacitors taller to achieve the required capacitance within a small area. As the process scales down, the lateral area occupied by each cell has to shrink, while its ability to store charge must be maintained. That is why capacitors keep getting taller within an increasingly narrow footprint.

But this approach is becoming more difficult. As the area shrinks further, maintaining capacitance and controlling leakage current become simultaneous challenges. These are not problems that automatically disappear by moving to the next node. The question becomes how much further the existing structure can scale.

That led to the idea of changing the cell arrangement from vertical to horizontal and stacking that structure in multiple layers, rather than continuing to make each cell smaller. It applies the NAND idea of increasing capacity through cell stacking to DRAM. Instead of simply making an existing capacitor taller, the aim is to increase capacity by changing the cell structure and the direction in which it is stacked.

Damnang: I understand 3D DRAM has been researched for a long time. When do you think it could actually be used?

Expert: A report last year mentioned 2033 as the timing for mass production. That is not an officially confirmed production schedule, however, and there are efforts to accelerate development.

Damnang: What is driving the push to develop it faster? Is it customer demand, or is there another reason?

Expert: The underlying issue is that scaling conventional DRAM keeps getting harder. Until now, progress has come from making cells smaller and moving to the next node. Whether that same approach can continue is a separate question. We therefore have to prepare not just the node currently in development, but also the structure that comes after it.

Vertical gate structures are another way to extend conventional DRAM. My understanding is that Samsung and SK hynix are considering vertical gate structures in the 4F² category. I do not work directly in that area, but the assessments I have heard suggest that the structure may be usable for one or two nodes, rather than continuing to scale across many generations.

That leaves the question of how to increase capacity and density after vertical gates. In that sense, 3D DRAM is not simply a research project for the distant future that we pursue when we have spare resources. If the existing structure reaches its scaling limit, we need something to follow it. That makes it a technology we have to develop, even though it is difficult.

Technical background | Editor’s supplement: What do 1T1C and 4F² mean?

1T1C describes a DRAM cell made up of one capacitor that stores charge and one transistor that controls access. In 4F², F refers to the minimum feature size of the technology, and 4F² expresses the cell area. It does not mean a stack of four layers.

Terminology | Three different forms of stacking in this report

3D DRAM refers to building the cell structure itself in multiple layers. In this conversation, 3D stacked DRAM refers to stacking memory and logic dies. The separation of cells and peripheral circuits discussed later means fabricating a cell wafer and a peripheral circuit wafer separately, then bonding them together. What is stacked and what is separated differ across these approaches.

02. China and the three major memory makers are taking different paths

Damnang: I have heard that China is also preparing for 3D DRAM. What do you know about its development progress or the technology gap?

Expert: What I encounter directly is patents. When we analyze relevant patents internally, we see YMTC and CXMT filing very actively in 3D technologies. I am not describing how far they have progressed toward mass production, but I get the impression that they are doing a great deal of preparation to establish a position in new structures.

My personal interpretation is that the major memory companies already hold extensive patent portfolios in conventional 2D DRAM. Following structures that the incumbents have developed over many years means getting past not just the technology, but also that patent base. By contrast, 3D DRAM is still at an early stage. I think the Chinese companies may be trying to secure patents and technology in new structures before the field becomes established.

Their bonding experience is also relevant. China has experience with approaches such as Xtacking that use bonding in NAND. Since bonding is also involved in 3D DRAM, there may be an effort to bring that NAND experience and confidence into a different memory structure.

When the conventional scaling path is constrained, there is a stronger reason to pursue a change in structure rather than simply follow that path. That is why I do not see China’s activity solely as an effort to catch up to the next conventional DRAM node. I see it as a search for a separate opportunity in new structures.

Damnang: Samsung is also developing 3D DRAM, as I understand it. How does its approach compare with SK hynix?

Expert: As far as I know, the three companies differ even in how they form the patterns. They may all use the term 3D DRAM, but they appear to be making different choices about how to build the structure and extend it to taller stacks.

Damnang: Oh, so even though they are all developing 3D DRAM, the manufacturing approaches are different?

Expert: I cannot discuss the details, but my understanding is that Samsung and SK hynix use different approaches to building up the hardmask layers.

I have heard that Micron is researching a different approach as well. From what I hear through equipment suppliers, it is working actively on 3D DRAM and intends to move directly to it without going through the vertical gate stage. It seems to have internal expertise in building multiple layers, but I do not know the specific method it uses.

That makes it difficult to put all three companies on a single process roadmap and say that one is a certain number of steps ahead. What I can say is that their manufacturing approaches and the paths they are taking to extend them are somewhat different.

Damnang’s interpretation

The important point in this discussion was not to choose a winner before one had been established. It was that the same technology label can cover different manufacturing paths and different limits on how high the structure can be stacked. Patent activity, implementing a structure, extending the stack, and achieving competitive mass production should not be treated as a single milestone. The next section on cleaning and metrology shows how these differences translate into practical development challenges.

03. Lateral etching and metrology constrain development speed

Damnang: What has to change in the existing processes or equipment as we move to 3D DRAM?

Expert: Etching was extremely important in conventional 2D DRAM. A major challenge was how deeply and precisely a structure could be formed within a small area. Deep etching has also remained important in NAND.

But in the 3D structures we are looking at, the cleaning side is becoming much more difficult. An area once considered relatively less challenging has become one of the most difficult. Here, cleaning does not simply mean washing a surface clean.

Damnang: Why does the cleaning side become so difficult?

Expert: We use chemicals to etch laterally inside the structure, and that work sits within the cleaning process area. Companies that previously made cleaning equipment are developing tools for this process. Work that would once have been considered part of etching is now being performed within the cleaning area.

The difficulty is therefore not just removing contamination. We have to etch horizontally inside the structure, and forming films in that space is also difficult. In addition to etching deeply from top to bottom, we now have to work sideways and form the required structures within those spaces.

This explanation is based on the process strategy we are considering. Since each company uses a different manufacturing approach, the process step and equipment used to perform a given function can differ. It does not mean that every company’s 3D DRAM will use the same cleaning process.

I also think metrology is one of the main reasons development is not moving faster.

Damnang: What makes metrology difficult?

Expert: If we build multiple layers and a problem occurs, we need to know which layer is affected and what went wrong. In the development work I see today, we rely heavily on cutting samples and examining them with TEM to see the interior.

Having a process that can build the structure does not mean we also have a way to validate it quickly. To find out which internal layer is wrong, we have to prepare another specimen and inspect a cross section. That process itself takes time, increases the number of wafers used in evaluation, and slows down how quickly we can see the results.

In process development, we need to examine the result before choosing the next set of conditions. The problem is that seeing the result takes a long time. So the challenge is not only how to fabricate the structure, but also how to measure and validate the defects inside it. I think we need metrology methods suited to these new structures.

Damnang: Could established metrology equipment companies such as KLA solve this problem?

Expert: An established company such as KLA could address it, but we should distinguish conventional inspection from metrology of these internal structures. The existence of inspection equipment suppliers does not mean that all the methods needed for this internal validation are already available. Within what I have encountered, there is still not much information on these new metrology approaches.

For 3D DRAM to advance, the equipment and methods for evaluating its structures have to develop alongside it. In that sense, I see a growing need and opportunity for new metrology equipment.

Technical background | Editor’s supplement: Seeing a cross section versus understanding a 3D structure

TEM stands for transmission electron microscopy. NIST explains that TEM and STEM are widely used in process development and failure analysis, but conventional imaging alone becomes less effective at characterizing shapes and defects in complex semiconductor structures. It is researching electron tomography methods that reconstruct structures in three dimensions.

This is general research background for understanding the metrology challenges discussed in the call. It does not mean that SK hynix has adopted these methods for 3D DRAM or that they have already solved the validation speed problem described by the expert.

Damnang’s interpretation

More important than the difficulty of fabrication alone was the fact that fabrication and validation belong to the same development cycle. Building the structure, examining its interior, finding problems, and adjusting process conditions all contribute to development time. When looking at equipment, I would start with the fabrication and measurement tasks required by a new structure, rather than with existing categories such as etching, cleaning, and inspection.

04. A different path: separating cells and peripheral circuits

Damnang: Are there any technologies besides 3D DRAM that you are following closely?

Expert: There is another technology attracting more attention alongside 3D DRAM. It is the approach I have been referring to as 2D POC.

Damnang: 2D POC? Is that a different structure from 3D DRAM?

Expert: POC stands for Peri on Cell. The terminology may differ by company, so it is better to describe it here as separating the cells and peripheral circuits.

Conventional DRAM puts the cells and peripheral circuits on the same wafer. This approach separates them: one wafer is made for the cells and another for the peripheral circuits, and the two wafers are then bonded together. It brings to DRAM the idea of fabricating cells and peripheral circuits separately and connecting them, as has been done in NAND.

That can free up more area for the cells and create a path to higher density and bit capacity. At the same time, the peripheral circuits can evolve independently of the cells. The important point is that we can retain existing cell technology and improve other parts without rebuilding the cells themselves into an entirely new 3D structure.

I think there is still considerable room to improve the peripheral circuits. Memory companies have developed cell technology for a long time, but some technologies used in advanced logic processes have not yet been fully brought into the peripheral circuits. That means improving the peripheral circuits alone can raise memory performance, rather than relying only on making the cells smaller.

From what I have heard, Samsung, Micron, and CXMT are actively pursuing this approach. Samsung has foundry and logic technology that it can draw on. Alongside research into 3D DRAM, these companies are preparing a path that further develops capabilities they already have in conventional DRAM. Recently, I have started to think this could become just as important as scaling to the next node.

Technical background | Editor’s supplement: Why not use the latest logic process directly for peripheral circuits?

Peripheral circuits include decoders that select addresses, sense amplifiers that read small differences in charge, and output buffers. imec explains that these circuits have different requirements, including speed, analog characteristics, operating voltage, and leakage current.

Process sequencing is another constraint. If the peripheral circuits are fabricated first on the same wafer, they must withstand the high temperature treatments used later to form the memory cells. In the conventional process example described by imec, they can be exposed to temperatures of 550 to 600°C for several hours. This makes it difficult to transfer an ordinary logic process directly.

Fabricating the peripheral circuits on a separate wafer can relax the thermal constraints imposed by cell fabrication. It also requires additional fabrication and bonding steps. This is general technical background on why separation creates an opportunity for independent optimization, not a description of a process adopted by a specific company.

Damnang: I see. The cells and peripheral circuits are made separately and then bonded. Could the hybrid bonding technology or equipment being prepared for HBM also be used here?

Expert: Hybrid bonding or fusion bonding are possible approaches to the joining step. The central point I am making is that the cells and peripheral circuits are made separately and then bonded. But we should not treat this as exactly the same problem as HBM bonding.

HBM involves handling and stacking individual dies. The separation of cells and peripheral circuits that I am describing uses wafer to wafer bonding. The unit being bonded is different, as is the experience behind the technology. I think bonding at the wafer level may be relatively less difficult.

Wafer to wafer hybrid bonding has already been used extensively in areas such as Sony’s image sensors. Memory companies also have experience with bonding in NAND. That gives this approach an existing foundation to draw on, compared with developing a completely new cell structure and manufacturing method from scratch.

The attraction is that a new DRAM can be built by combining existing cell technology, bonding that companies already have experience with, and peripheral circuits that still have room to improve. Rather than treating everything under the same bonding label, it makes more sense to distinguish what is being bonded and which existing capabilities can be used.

Terminology note

Hybrid bonding and fusion bonding were mentioned above as examples of joining approaches. This does not mean that their processes or electrical interconnect configurations are the same.

Damnang: How is SK hynix preparing for this approach?

Expert: My personal view is that SK hynix began paying more attention to this area a little late. Other companies were already preparing for it, while we placed more emphasis on scaling conventional DRAM. I felt there was a strong inclination to keep pushing toward 1d and beyond because further scaling was still possible.

But being able to scale a technology and producing it at a viable unit cost are different things. If further scaling requires better EUV tools, such as High NA EUV, and substantially higher process costs, we have to ask again whether shrinking the node that far is the best approach.

If separating the cells and peripheral circuits offers another route to improvement, we have to compare the two. Retaining existing cells and improving performance through the peripheral circuits could be more suitable than pushing the existing structure to its scaling limit. That is why it is becoming harder to regard one path as the only answer.

Of course, scaling work that is already well advanced cannot simply be abandoned. My understanding is that it continues while new approaches, including cell and peripheral circuit separation and 3D DRAM, are prepared in parallel. More people are being assigned to these areas, but staff and resources are finite. There is a decision to make between maintaining every option and choosing where to concentrate.

The attitude toward process transitions also feels somewhat different. Previously, the emphasis was on how quickly we could move to the next node. Now, because new investments in etch and EUV equipment are so expensive, there seems to be more emphasis on making the most of the existing base. That does not mean stopping development. It means weighing the benefits of a node transition against the additional cost.

Damnang: Is this technology only for conventional DRAM, or could it also be used in HBM?

Expert: I see a strong possibility of using cell and peripheral circuit separation in HBM because it does not require a cell structure that is completely different from conventional DRAM. The technology used to make conventional DRAM is connected to the DRAM technology inside HBM. An approach that retains existing cells is therefore relatively straightforward to consider for HBM as well.

3D DRAM, in which the cells themselves are built in multiple layers, requires more thought. We have to consider whether it makes sense to form TSVs through a structure whose cells are already stacked in 3D, and then stack those structures again to make HBM. A way to increase capacity at the cell level does not automatically determine the packaging that follows.

That is why I am paying attention to the potential of approaches such as separating cells and peripheral circuits when considering both the cell structure and the package. Moving to an entirely new 3D cell structure and improving conventional DRAM for use in HBM are different paths.

The DRAM technology inside HBM also has to keep advancing. From that perspective, my personal view is that separating cells and peripheral circuits could become more important next year than 1d itself. There is increasingly more to examine than the name of the node.

Damnang’s interpretation

This changed the question. We need to ask not only who reaches the next node first, but also which part of the memory benefits most from being changed: the cells or the peripheral circuits. Separation does not mean abandoning scaling, nor does it necessarily replace 3D DRAM. It means distinguishing the paths to better area efficiency and peripheral circuit performance, then comparing them alongside fabrication and bonding costs and the implications for HBM packaging.

05. SK hynix draws strength from collaboration and customer support

Damnang: From your perspective as an employee, what is the atmosphere at the company like these days?

Expert: The atmosphere feels positive. People work hard and care about the company. But what I see as particularly relevant to competitiveness is not just morale; it is how people collaborate.

Information is shared readily when we work with other teams. When we ask for material, they do not just provide a small part of the result. They also share the evaluation data behind it. There is a tendency to see the work as something we need to solve together, rather than drawing a strict line between my job and another team’s job.

In process development, you need to know what another team has tried and what results it obtained before you can move forward. Being able to get that material quickly, including the evaluation details, helps the work progress. That is something I appreciate in day to day development.

It would be difficult to explain SK hynix’s lead in HBM through one specific technology alone, but I believe this collaborative culture has contributed to development speed and competitiveness. That is my personal assessment based on the organization I have experienced.

Damnang: What matters most in meeting the needs of customers such as NVIDIA?

Expert: I feel SK hynix has a strong commitment to adapting to the customer. Working hard on the technology is a given. When a customer raises a problem, the approach is to stay close to the customer and keep working until it is resolved.

In one example I heard about, quality engineers were sent to the customer site and support continued through rotations every two weeks, rather than ending after a single business trip. The next group would take over until the problem was solved. I think that kind of sustained, close customer support is a strength.

It is also important to ask what the customer needs and look for what else we can do. Delivering the requested specifications and seeing problems through to resolution in actual use are connected. I think we should consider that approach to support alongside the technology itself.

Damnang: What about working with other companies, such as TSMC? Does that generally work well?

Expert: I do not work directly with TSMC, but I have not heard much from the design side about major difficulties. I hear more about the challenges of meeting NVIDIA’s requirements. The relationships are different: NVIDIA is our customer, whereas SK hynix is the customer from TSMC’s perspective.

Damnang: How are requests from customers who want 4 high HBM received?

Expert: I heard from the design side that there are circuits that allow groups of four layers to be validated separately. For example, suppose a problem occurs in one group of four layers while making an 8 high product. If the usable group of four can be identified and sold as a product with fewer layers, the outcome is different from having to discard the entire stack.

The explanation was that this could be positive if customers want such a product, because it would generate revenue from material that previously could not be sold. I do not know whether other companies use the same approach.

Damnang: Have you noticed any other changes inside the company recently?

Expert: Yes, I have noticed changes. Around this summer, I felt a stronger push to become a global company. English began appearing first in internal emails, and everyday information such as cafeteria menus was also being changed to English.

It is not just a change in wording. I see international interns in the research institute. That gives me the impression that the company is preparing to hire and work with more people from outside Korea.

There are also efforts to recruit talent in the United States. Bringing in the people you need and creating an environment in which they can actually work have to go together. That is how I interpret these changes.

Damnang’s interpretation

In the same interview, the expert expressed confidence in the company’s collaborative culture while saying earlier that its strategic response to cell and peripheral circuit separation had been late. Those views are not contradictory. Organizational strengths and the challenges remaining in individual technologies need to be considered together. Customer support also came through as concrete behavior, including data sharing and a sustained presence by quality engineers at customer sites, rather than as an abstract cultural claim.

06. Hybrid bonding: a gap in sample development progress

Damnang: Where does SK hynix stand in developing hybrid bonding for HBM?

Expert: From what I have heard, SK hynix is still facing technical difficulties in developing hybrid bonding for HBM. My understanding is that samples using hybrid bonding have not yet been produced.

By contrast, there have been reports that Samsung has already sent samples to customers. Internally, people are watching Samsung’s progress closely, with a sense of concern about falling behind.

Damnang’s interpretation

At the time of the interview, my understanding was that Samsung had produced HBM4 and HBM4E samples using hybrid bonding. The expert, meanwhile, said that SK hynix’s hybrid bonding samples had not yet been produced. Taken together, these points suggest a technology gap between Samsung and SK hynix in HBM hybrid bonding development at that time.

Competitiveness built through mass production of existing HBM and readiness for a new bonding process are separate matters. SK hynix’s lead in existing HBM does not, by itself, establish the same lead in hybrid bonding.

This is a judgment about sample development progress. The discussion also included reservations about the performance of Samsung’s samples, so I would not extend that judgment directly to an advantage in production yield or customer qualification.

Interview reference: original transcript, 00:45 to 00:50. Comparison based on the expert’s comments and Damnang’s understanding of sample availability at the time of the interview.

07. From process roadmaps to the AI memory hierarchy

Damnang: I attended the forum as well. How is the company discussing its future direction internally?

Expert: There is an annual future forum where the company shares its direction. In the past, there was a lot of discussion about which technology nodes to pursue and which roadmaps to prepare. This year, I felt much more attention was being given to what SK hynix should do within AI architectures.

For example, the discussion includes proposing new memory tiers and establishing a role within them. There seems to be more discussion of what a memory company can propose within the architecture of AI infrastructure, including a tier such as HBF between DRAM and NAND. That is a broader area of interest than developing the next DRAM node.

I also see active recruitment of design engineers in connection with that direction. There was a posting for hundreds of entry level design roles, which struck me as a different scale from before. I hear that the design organization is running short of space, and experienced hiring also seems active.

I interpret these changes as efforts to fill capability gaps so that the company can take on new roles. From what I can see, its focus is expanding beyond competition in process nodes to the question of what kinds of structures it can propose within AI infrastructure.

Damnang: This is just my own thought, but what about working with Intel?

Expert: SK hynix does not have a foundry business alongside its memory operations in the same way Samsung does, so I think there is a lot to consider in securing the necessary logic technology and manufacturing capabilities through collaboration. Being strong in memory and implementing the required designs on another company’s process are capabilities that have to be prepared together.

Regarding Intel, I heard from someone on the design side that there was an evaluation of whether its process could be used for the base die. The explanation was that an evaluation request had come from the base die team. My understanding is not that a decision had been made, but that the feasibility was being examined.

I understand that moving a design already developed for a TSMC process to another foundry requires considerable effort. It is not simply a matter of changing factories; there are many things the design team needs to reassess. So the key point in what I heard was not that Intel would be used, but that its use was being evaluated.

Damnang | The difference between evaluating a process and adopting it

From a design perspective, changing foundries also changes the PDK. It is not a matter of sending the existing design files to another factory. Design work and validation specific to the target process are required. That is why evaluating a candidate process and adopting it in an actual product should be distinguished.

Technical background | Editor’s supplement: What does a change in PDK mean?

The public SkyWater PDK documentation covers design rules, device models, standard cell and input/output libraries, interconnect parasitic extraction, and physical verification. It illustrates that a PDK is not merely a document naming a process, but a concrete technical foundation for design and validation.

The point that a process change also changes the design work can be understood in terms of that underlying foundation. The public PDK is used here to explain the general concept, not to compare Intel’s or TSMC’s private PDKs or quantify the effort required to move between them.

Damnang’s technical question | What would customers need to change to use HBF?

Later in the conversation, I distinguished the need for HBF from its actual adoption. Even in a use case dominated by reads with relatively predictable access, would the benefits be large enough for a customer to change the operating system or system behavior to accommodate a new memory tier? This was a usage scenario and question I raised, not a statement of confirmed HBF specifications or validation results.

Damnang’s interpretation

Proposing a new memory tier has to be followed by investment in design talent and external collaboration. Expanding the workforce, evaluating a candidate process, and adopting it in a product are different stages, but they support the same direction. Understanding a memory company’s ambition to play a larger role in AI systems requires looking beyond the concepts it announces to how it builds the capabilities needed to implement them.

08. Solidigm NAND and continuity in process development

Damnang: I am also curious about Solidigm. How do you view it as someone who develops processes?

Expert: Solidigm and SK hynix use different technology foundations to manufacture NAND. Solidigm’s NAND, inherited from Intel, uses floating gate technology, while SK hynix uses a CTF approach. Intel developed technology that differed from other NAND manufacturers, so being in the same NAND business does not mean that process development experience can simply be shared without changes.

That was the point that concerned me. Having people who developed NAND processes on one side does not mean they can immediately support a different kind of NAND technology. SK hynix’s existing process development capabilities and the technology Solidigm has carried forward need to be considered separately.

When I heard about expanding production, my first question was less about the factory itself than about who would develop the next process upgrade. Producing with the technology available today and advancing that technology into later generations are different tasks. Even if the current product can be manufactured, people and an organization are still needed to continue development.

That is why I thought a production expansion based on a different technology would also require consideration of a dedicated development team. Since the processes differ, we should not assume that the existing development organization at headquarters can simply take over. The question I had was how to ensure continuity in technology development, not just how to increase production capacity.

Damnang’s interpretation

I read this as a question from a process development perspective rather than as a judgment on a specific factory plan. Increasing production capacity and preparing the next generation of technology are not the same task. Even within the same corporate group, NAND businesses with different technology foundations need to be assessed not only by the scale of their facilities but also by the development organizations that will keep advancing those technologies.

Closing. Evaluate the same memory company technology by technology

It is difficult to reduce this conversation to either optimism or concern about SK hynix. The expert identified collaboration and customer support as strengths while also discussing the strategic choices around separating cells and peripheral circuits and the challenges of hybrid bonding.

The criteria for evaluating the technology also changed. For 3D DRAM, the issue was not just the idea of stacking cells, but how quickly the interior of a structure formed through lateral processing could be examined. For cell and peripheral circuit separation, the question was which part to develop independently, rather than simply which smaller node to pursue. Connecting either approach to HBM required looking further ahead to TSVs and packaging.

The same applies to company competitiveness. A statement that a company’s process technology is strong encompasses structural choices, development speed, equipment investment, collaboration across departments, and customer support. A lead in one technology does not automatically explain its readiness in another.

What I want to examine more closely from here is which structures companies choose, whether methods to evaluate those structures are ready, and where the cost and performance benefits arise relative to existing processes. I thought I knew something about memory, but this call helped me break those questions down much more precisely.